Bias-Source Strong PUF Circuit for Stable Anti-ML Responses

The PUF circuit is segmented into n delay modules, each processing a portion of the challenge signal independently. Each delay module contains multiple transmission paths that are segmented and recombined through interconnection modules, creating complexity without requiring multiple complete PUF instances. This segmentation allows the system to achieve high anti-ML attack capacity while controlling hardware overhead.

The patent implements a nested structure where n delay modules are processed through n-1 interconnection modules, with each interconnection module taking outputs from previous modules and feeding them into subsequent modules. This nested processing architecture allows the system to achieve exponential complexity growth (anti-ML capacity) without linear growth in hardware components, as each module reuses and transforms outputs from previous stages.

The patent merges the outputs of n delay modules through a systematic combination process using interconnection modules and a final XOR gate. Instead of using multiple independent PUF outputs that may fluctuate independently, the system combines all delay module outputs through a unified processing path that includes arbitration and final XOR aggregation. This merging process ensures that temperature and voltage variations affecting individual modules are averaged out, maintaining output stability while preserving anti-ML attack capacity.

The arbitration process in the patent implements a feedback mechanism where the outputs of multiple delay modules are continuously monitored and combined through the interconnection modules. The system uses the challenge signal to control the selection and combination of outputs, creating a feedback loop that ensures consistent response generation despite environmental variations. This feedback mechanism maintains stability by ensuring that all modules contribute to the final output in a controlled manner.

The patent implements dynamic challenge-response mapping where the transmission paths through the delay modules are controlled by the challenge signal itself. The challenge bits dynamically select which transmission paths are activated in each delay module, creating a dynamic and adaptive mapping relationship. This dynamic approach increases anti-ML attack capacity because the mapping changes based on the challenge input, while the underlying hardware structure remains relatively simple and static.

The system changes the effective parameters of the challenge-response mapping by using the challenge signal to control transmission path selection in each delay module. The same hardware structure can produce different mapping complexities depending on the challenge input, allowing the system to achieve high anti-ML attack capacity without permanently increasing hardware complexity. The parameter changes are achieved through controlled signal routing rather than physical structural changes.