Bias-Stabilized Relaxation Oscillator With Low Frequency Spread
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Solution Overview
Problem
Conventional relaxation oscillators require a current source, leading to increased silicon area and power consumption, and suffer from frequency variations due to comparator propagation delays across process corners, affecting signal fidelity.
Innovation Solution
A relaxation oscillator design that eliminates the need for a current source by using inverter-comparator stages with bias generation through PMOS and NMOS transistors, generating bias voltages to stabilize comparator trip points and reduce frequency spread across process and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a current source is used to operate comparators in conventional relaxation oscillators, then the comparators can function properly, but the silicon area and power consumption increase considerably
Solution Approach 1:
The patent removes the current source from the relaxation oscillator circuit, extracting the problematic component that caused area and power consumption issues. The comparators are made to function without requiring a dedicated current source, thereby eliminating the source of the contradiction.
Solution Approach 2:
The comparators are designed to operate using the existing voltage signals in the circuit without requiring an external current source. The circuit components themselves provide the necessary operating conditions, making the system self-sufficient and eliminating the need for additional area-consuming components.
2Productivity
If conventional comparators are used in relaxation oscillators, then the oscillation function is achieved, but propagation delays vary substantially across process corners causing frequency variations
Solution Approach 1:
The patent implements feedback mechanisms through the interconnected comparator stages where the output of one comparator feeds into the next stage. This feedback arrangement compensates for propagation delay variations, as the cumulative effect of multiple stages with varying delays results in more consistent overall timing and frequency across different process corners.
Solution Approach 2:
The patent combines multiple comparator stages into a single integrated oscillation circuit where the comparators work together in sequence. By merging the functionality of multiple comparators with feedback connections, the circuit achieves frequency consistency that overcomes the individual comparator propagation delay variations.
3Productivity
If conventional relaxation oscillators are integrated into SoC, then oscillation signals are generated, but area and power consumption are increased
Solution Approach 1:
The patent removes the current source component from the oscillator circuit, extracting the element that was primarily responsible for high power consumption. This allows the oscillator to generate signals with significantly reduced power requirements, making it suitable for power-sensitive SoC applications.
Solution Approach 2:
The patent changes the operating parameters of the comparator stages by eliminating the current source and using voltage-based operation instead. This parameter change fundamentally alters the power consumption characteristics while maintaining the oscillation generation capability.
Data Source
AI summary
A relaxation oscillator for generating an output clock signal includes a RC circuit, a bias generation stage, first and second comparator stages, and a logic circuit. The RC circuit generates first and second comparator input signals that are transmitted to the first and second comparator stages. The bias generation stage generates first and second bias voltages that are provided to each of the first and second comparator stages. The first and second comparator stages generate first and second comparator output signals, respectively, based on the first and second comparator input signals and the first and second bias voltages. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.