Bias Voltage Circuit With Threshold Cancellation for Stable 1/2 VDD
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional bias voltage generating devices face challenges in achieving accurate and stable output voltages due to temperature-dependent threshold voltages of transistors, leading to variations in the output voltage, especially when generating ½VDD from a supply voltage like 1.8V.
Innovation Solution
The proposed bias voltage generating device employs diode-connected transistor pairs and impedance elements to create a reference bias section and a driving section, where the transistor pairs are selected such that their threshold voltages cancel out, ensuring a stable output voltage of ½VDD with minimal error, and includes additional configurations with sense and gain sections to further stabilize the output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bias voltage generating devices are used, then the device structure is simple, but the output voltage stability deteriorates due to temperature-dependent threshold voltages
Solution Approach 1:
The patent changes the electrical parameters of the transistor pairs by selecting specific threshold voltage values that satisfy the cancellation condition. The first and second transistor pairs are configured with threshold voltages that, when combined with the third and fourth transistor pairs, result in net threshold voltage cancellation, thereby stabilizing the output bias voltage against temperature variations.
Solution Approach 2:
The patent creates a composite transistor configuration by combining four different transistor pairs (first, second, third, and fourth pairs) with specifically selected threshold voltages. This composite structure leverages the complementary threshold voltage characteristics of the different transistor pairs to achieve overall threshold voltage cancellation and improved output stability.
2Measurement precision
If transistor pairs with canceling threshold voltages are used, then output voltage accuracy improves, but device complexity increases due to additional configurations
Solution Approach 1:
The patent achieves high output voltage accuracy by carefully selecting and configuring transistor pairs with specific threshold voltage parameters. The first transistor pair has threshold voltages that are complementary to the second transistor pair, and similarly the third and fourth transistor pairs are configured to cancel each other's threshold voltage effects, resulting in net zero threshold voltage impact on the output.
Solution Approach 2:
The patent employs a symmetric configuration where the third and fourth transistor pairs replicate the threshold voltage cancellation principle of the first and second transistor pairs. This copying of the cancellation mechanism across multiple transistor pair configurations reinforces the output stability and accuracy while maintaining a systematic design approach.
3Reliability
If additional sense and gain sections are added, then output voltage stability further improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the bias voltage generating device into distinct functional sections: the first and second transistor pairs form one functional unit for threshold voltage cancellation, while the third and fourth transistor pairs form another unit. Additionally, sense sections and gain sections are segregated as separate functional blocks, allowing for modular manufacturing and testing while achieving enhanced output stability.
Data Source
AI summary
The present disclosure provides a bias generating device and a method for generating bias. A bias generating device includes a first diode-connected transistor pair connected to receive a first voltage; a second diode-connected transistor pair connected to receive a second voltage; and a first transistor pair connected to the first diode-connected transistor pair and the second diode-connected transistor pair. The first transistor pair is configured to generate a third voltage in response to the first voltage and the second voltage.


