Bias-Controlled Clock Timing Cells for Supply-Stable Memory Clocks
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Solution Overview
Problem
Memory devices experience significant clock jitter due to variations in supply voltage and current, which can disrupt the synchronization of read and write operations across multiple memory cells, leading to operational issues.
Innovation Solution
The implementation of bias-controlled clock timing cells, which adjust the timing of clock signals using bias signals to reduce the number of delay cells required, thereby minimizing power supply sensitivity and clock jitter. These cells include a bias-controlled inverter and a parallel inverter, with adjustable drive strength to alter the timing of clock edges, allowing for precise control over the duty cycle and delay of clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delay cells are used to adjust clock timing, then timing precision is improved, but clock jitter and power supply sensitivity increase
Solution Approach 1:
The patent changes the control parameter from voltage-based delay cells to current-based timing adjustment. By using bias current signals to control the timing of clock edges, the system achieves precise timing control while reducing sensitivity to power supply voltage variations, thereby reducing clock jitter.
Solution Approach 2:
The patent replaces the traditional voltage-controlled delay cell mechanism with a current-controlled timing mechanism. The bias-controlled inverter uses current signals to directly adjust clock edge timing, substituting the mechanical/electrical voltage delay mechanism with a more stable current-based control system that is less sensitive to power supply variations.
2Measurement precision
If multiple delay cells are used to adjust clock timing, then timing precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the timing adjustment function into a single bias-controlled inverter stage rather than using multiple separate delay cells. The bias current signal simultaneously controls both rising and falling edge timing, combining multiple timing control functions into one integrated circuit element, thereby reducing overall device complexity.
Solution Approach 2:
The bias-controlled inverter performs multiple functions: it adjusts rising edge timing, adjusts falling edge timing, and compensates for duty cycle variations, all through a single circuit element controlled by bias current signals. This multi-functionality eliminates the need for separate delay cells for each timing adjustment.
3Reliability
If bias-controlled timing cells are used, then power supply sensitivity is reduced, but control complexity increases
Solution Approach 1:
The bias-controlled inverter automatically adjusts its timing characteristics based on the applied bias current signal. The circuit self-regulates the clock edge timing by responding to current variations, eliminating the need for complex external control mechanisms or multiple adjustment stages. The timing control is inherent to the circuit's operation under different bias conditions.
Data Source
AI summary
Clock signal timing cells, clock signal timing circuits, clock circuits, memory devices, systems, and method for altering the timing of a clock signal are disclosed. An example method for altering the timing of an output signal provided responsive to an input clock signal includes adjusting a transition of an edge of the output signal from one voltage level to another based at least in part on a bias signal. An example clock signal timing cell includes an inverter and a bias controlled inverter coupled in parallel to the inverter. The bias controlled circuit is configured to provide an output signal wherein a transition of a clock edge of the output signal between first and second voltage levels is based at least in part on a bias signal.