Bias-Tuned Cascode Distributed Amplifier for Linearity-Bandwidth Tradeoff

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current broadband gallium nitride (GaN) distributed amplifiers face a trade-off between linearity and gain-bandwidth, limiting high-linearity DAs to less than 20 GHz microwave frequencies.

Innovation Solution

The distributed amplifier design incorporates a cascode configuration with a common-drain cascode amplifier cell, featuring a main transistor and a cascode transistor, along with an input transistor in a common-drain configuration, coupled with current source circuitry for bias tuning, which enhances linearity and gain-bandwidth by adjusting current flow through the current source control terminal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If efforts are made to increase linearity in distributed amplifiers, then third-order intercept point improves, but gain-bandwidth is reduced

Engineering Contradiction:
ImprovelinearityVSAvoidgain-bandwidth
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The amplifier is divided into multiple identical amplifier cells connected in parallel, each contributing to the overall gain while maintaining linearity. The segmentation allows the amplifier to achieve high linearity through the distributed architecture without sacrificing gain-bandwidth product

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The amplifier employs dynamic bias tuning through current source circuitry that can adjust operating conditions in real-time. This dynamic control enables optimization of both linearity and gain-bandwidth based on operating requirements, resolving the static trade-off between these parameters

Inventive Principle:
Principle #15Dynamics

2Speed

If distributed amplifier operates at millimeter-wave frequencies, then frequency range extends, but maintaining high linearity becomes difficult

Engineering Contradiction:
Improvefrequency rangeVSAvoidlinearity
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The amplifier uses parameter tuning through bias control circuitry to optimize performance at millimeter-wave frequencies. By dynamically adjusting bias conditions and operating parameters, the amplifier maintains high linearity (IP3) across the extended frequency range up to 40 GHz and beyond

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Multiple identical amplifier cells are used in a distributed configuration, where each cell is a precise copy of the others. This copying approach ensures consistent linearity performance across all frequency bands, enabling millimeter-wave operation while maintaining high IP3

Inventive Principle:
Principle #26Copying

3Measurement precision

If cascode configuration is used to improve linearity, then third-order intercept point increases, but power dissipation increases

Engineering Contradiction:
ImprovelinearityVSAvoidpower dissipation
Core Design Contradiction:
Measurement precisionVSLoss of energy

Solution Approach 1:

The bias tuning circuitry provides partial adjustment capability, allowing optimization of linearity only when needed. The system can operate in a balanced mode that achieves sufficient linearity improvement without the full power penalty of aggressive bias tuning, thus reducing overall power dissipation

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10340858B2Linearized distributed amplifier architecture
Publication Date: 2019.07.02 QORVO US INC
  • US10340858B2 patent drawing
  • US10340858B2 patent drawing
  • US10340858B2 patent drawing

AI summary

A distributed amplifier (DA) is disclosed. The DA includes a first plurality of inductive elements coupled in series forming a first plurality of connection nodes. The DA also includes a second plurality of inductive elements coupled in series forming a second plurality of connection nodes. The DA further includes a plurality of amplifier cells that each has a main transistor and a cascode transistor coupled into a cascode configuration. The cascode transistor has a current input coupled to a corresponding one of the first plurality of connection nodes. An input transistor has a control terminal coupled to a corresponding one of the second plurality of connection nodes, a current input terminal configured to provide a bias tuning for the DA, and a third current output terminal coupled to a control terminal of the main transistor and configured to provide a separate bias tuning for the DA.