Binary-Weighted Bias Unit Circuit for Low-Power Charge Transfer MACs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multiplier-accumulator architectures for machine learning applications face challenges in scalability and power consumption due to synchronous operation and increased gate complexity, particularly in performing multiply-accumulate operations for large matrices, which results in high power dissipation and inefficiency.
Innovation Solution
A scalable asynchronous multiplier-accumulator architecture utilizing a common charge transfer bus for multiplier-accumulator, bias, and analog-to-digital converter unit elements, employing NAND groups and charge transfer capacitors to minimize displacement currents and power consumption by enabling asynchronous operation and sharing of positive and negative charge transfer lines, along with a successive approximation ADC for efficient digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If synchronous clocked stages are used for multiplier operation, then operation timing is controlled, but power dissipation increases
Solution Approach 1:
The patent transitions from static synchronous clocked operation to dynamic asynchronous operation where the system adapts its timing based on actual computation completion. The multiplier-accumulator uses dynamic timing signals that are generated based on when data is ready, rather than being forced to operate on a fixed clock cycle, thereby reducing unnecessary switching activity and power dissipation.
Solution Approach 2:
The patent eliminates periodic clocking in favor of event-driven operation. Instead of continuous periodic clock signals that cause repeated switching regardless of computational need, the system uses sporadic timing signals generated only when multiplication or accumulation operations are completed, significantly reducing dynamic power consumption.
2Productivity
If large matrix multiply-accumulate operations are performed, then computational capability increases, but gate complexity increases as n2
Solution Approach 1:
The patent segments the large matrix multiplication task into multiple smaller unit element stages. Each stage handles a portion of the computation (individual multiplication and accumulation operations), and the results are progressively accumulated. This modular segmentation allows large n×n matrix operations to be performed by cascading multiple simple UE stages rather than requiring a single complex gate structure.
Solution Approach 2:
The patent implements a hierarchical structure where unit elements are nested within stages, and stages are cascaded to form the complete MAC architecture. Each UE contains nested logic for multiplication and accumulation, and multiple UEs are nested in series to handle increasingly larger matrix operations, allowing scalable computation without proportionally increasing individual gate complexity.
3Measurement precision
If multiple adders are used for multiply-accumulate operations, then accumulation accuracy improves, but power dissipation increases
Solution Approach 1:
The patent merges the multiplication and accumulation functions into a single integrated unit element stage. Instead of separate multiplier circuits followed by separate adder trees, the UE combines both operations in one stage with shared logic and timing, reducing the total number of active components and their associated power consumption while maintaining full accumulate precision through proper charge transfer and summation mechanisms.
4Loss of energy
If asynchronous operation is implemented, then power consumption decreases, but timing control becomes more difficult
Solution Approach 1:
The patent implements feedback mechanisms where completion signals from multiplication operations are fed back to control the timing of subsequent accumulation operations. The carry signal and timing signals are generated based on actual operation completion rather than external clock edges, providing automatic timing control that adapts to the actual computational state, making asynchronous operation manageable without external clock synchronization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture reduces power consumption by minimizing displacement currents and allows for scalable, efficient multiply-accumulate operations, especially when kernel coefficients are static, while maintaining accuracy and flexibility in handling various matrix sizes and operations.
Implementation Method 1
each NAND gate having a positive output coupled through a binary weighted positive charge transfer capacitor to a unique positive charge transfer line and a binary weighted negative output coupled through a negative charge transfer capacitor to a unique negative charge transfer line
Implementation Method 2
a first plurality of MAC unit elements (MAC UEs) performing multiply-accumulate operations on X and W digital inputs, each MAC UE providing a result as a charge transferred to a differential charge transfer bus
Data Source
AI summary
A Bias Unit Element (UE) comprises NAND gates with complementary outputs, the complementary outputs coupled through a charge transfer capacitor to a differential charge transfer bus comprising positive charge transfer lines and negative charge transfer lines. Each line of the differential charge transfer bus has a particular binary weighted line weight, such as 1, 2, 4, 2, 4, 8, and 4, 8, 16. Digital bias inputs are provided to the Bias UE NAND gate inputs, with a clear bit to initialize charge, and a sign input for enabling one of a positive Bias UE or negative Bias UE. A low-to-high transition causes a transfer of charge to the binary weighted charge transfer bus, thereby adding or subtracting a bias value from the charge transfer bus.