Bias-Controlled VCO Delay Cells for Stable Fast PLL Synchronization

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Solution Overview

Problem

Conventional Phase Locked Loop (PLL) circuits in semiconductor integrated circuits face challenges in achieving operational stability and short locking times due to the sensitivity of voltage-controlled oscillators to voltage variations, which affects their frequency band and performance.

Innovation Solution

A phase synchronization apparatus that includes a voltage-controlled oscillator with multiple delay cells and a bias generation unit, which generates pull-up and pull-down bias voltages based on control signals to stabilize the oscillator's operation, allowing for a small gain and a wide usable frequency band, thereby improving operational stability and reducing locking time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a voltage controlled oscillator having a large gain is used, then short locking times are achieved, but frequency band becomes sensitive to voltage variations and operational stability degrades

Engineering Contradiction:
Improvelocking timeVSAvoidoperational stability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent changes the operating parameters of the voltage controlled oscillator by introducing bias control signals that adjust the gain of the VCO. By dynamically changing the gain parameter based on operational conditions, the system achieves short locking times when high gain is applied while maintaining operational stability when lower gain is used, thus resolving the contradiction between locking time and operational stability.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a voltage controlled oscillator having a small gain is used, then operational stability is improved, but locking time becomes longer and usable frequency band becomes narrower

Engineering Contradiction:
Improveoperational stabilityVSAvoidlocking time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent makes the gain of the voltage controlled oscillator dynamic rather than fixed. The bias generation unit adjusts the gain according to operational requirements, allowing the system to switch between high gain (for fast locking) and low gain (for stability) modes. This dynamic adjustment resolves the contradiction by adapting the gain parameter to different operational phases.

Inventive Principle:
Principle #15Dynamics

3Reliability

If a voltage controlled oscillator having a small gain is used, then operational stability is improved, but usable frequency band becomes narrower

Engineering Contradiction:
Improveoperational stabilityVSAvoidusable frequency band
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent changes the gain parameter of the voltage controlled oscillator dynamically to expand the usable frequency band while maintaining operational stability. By adjusting the gain according to the desired frequency range, the system can operate stably across a wider frequency band, resolving the contradiction between stability and frequency band adaptability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7791384B2Phase synchronization apparatus
Publication Date: 2010.09.07 SK HYNIX INC
  • US7791384B2 patent drawing
  • US7791384B2 patent drawing
  • US7791384B2 patent drawing

AI summary

A phase synchronization apparatus includes a bias control unit configured to sequentially delay an input clock signal to generate bias control signals having multiple bits, a bias generation unit configured to generate a pull-up bias voltage having a level that corresponds to logical values of the bias control signals, and to generate a pull-down bias voltage in response to a control signal; and a voltage controlled oscillator configured to include a plurality of delay cells respectively having a pull-up terminal and a pull-down terminal to generate an output clock signal in response to the control voltage, wherein the pull-up bias voltage is supplied to the pull-up terminals of the respective delay cells and the pull-down bias voltage is supplied to the pull-down terminals of the respective delay cells.