Bias Voltage Controller for DRAM Power-Off Leakage
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Solution Overview
Problem
Dynamic random access memory (DRAM) cells experience minority carrier leakage during power-off mode, leading to data loss and reduced refresh characteristics due to bias voltage transitions exceeding storage node voltage, causing charge leakage and voltage shifts.
Innovation Solution
Implementing a bias voltage controller that transitions the bias voltage to ground at a controlled rate, ensuring it remains less than or equal to the storage node voltage, and using capacitors to slow down the decay, thereby minimizing minority carrier leakage by maintaining the bias voltage below the storage node voltage during power-off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the bias voltage transitions to ground during power-off mode, then the power consumption is reduced, but the bias voltage exceeds the storage node voltage causing minority carrier leakage and data loss
Solution Approach 1:
The patent applies preliminary action by transitioning the bias voltage to ground in a controlled sequence before complete power-off, ensuring it remains below the storage node voltage throughout the transition. This prevents minority carrier leakage while still achieving power reduction, as the bias voltage is carefully managed during the power-down phase rather than simply turning off all voltages simultaneously
Solution Approach 2:
The patent implements dynamics by making the bias voltage transition dynamic and time-dependent rather than static. The bias voltage is allowed to float or transition at a controlled rate during power-off, adapting its level relative to the storage node voltage to prevent leakage while enabling power savings. This dynamic approach replaces the static on/off voltage control
2Reliability
If the bias voltage is maintained at high level during power-off, then data retention is improved, but power consumption increases and refresh frequency requirements increase
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bias voltage level during power-off mode rather than maintaining it at a fixed high level. The bias voltage transitions to a lower level or floats, changing its parameter state to prevent minority carrier leakage while still preserving data integrity. This parameter adjustment reduces the voltage differential that causes leakage without completely eliminating data retention
3Speed
If rapid voltage transition is used during power-off, then the power-off speed is improved, but voltage shifts exceed storage node voltage causing charge leakage
Solution Approach 1:
The patent applies preliminary action by initiating a controlled voltage transition sequence that prepares the bias voltage to follow the storage node voltage during power-off. This preliminary control prevents the bias voltage from exceeding the storage node voltage even during rapid transitions, maintaining charge retention while achieving fast power-off through careful timing and voltage sequencing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents minority carrier leakage, reducing data loss and improving refresh characteristics by maintaining the bias voltage at or below the storage node voltage, thus extending the retention ability of storage nodes and reducing the frequency of timed refresh cycles.
Implementation Method 1
DRAM cells experience minority carrier leakage during power-off mode, leading to data loss and reduced refresh characteristics due to bias voltage transitions exceeding storage node voltage
Implementation Method 2
using capacitors to slow down the decay, thereby minimizing minority carrier leakage by maintaining the bias voltage below the storage node voltage during power-off
Data Source
AI summary
Some embodiments include apparatus, systems, and methods having a voltage generator to generate a voltage, a memory cell including a storage node associated with a storage node voltage, and a power controller to provide a signal to the voltage generator such that the voltage generated by the voltage generator rises from a voltage less than a reference voltage to a voltage less than the storage node voltage, and such that the voltage generated by the voltage generator is less than or equal to the storage node voltage, at least partially in response to the apparatus entering into a mode. Other embodiments are described.