Bias Voltage Generation Circuit for High-Voltage MOS Integration

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving high integration and reduced leakage characteristics while operating at power voltages higher than the breakdown voltage of individual elements, often leading to increased process complexity and potential damage.

Innovation Solution

A semiconductor device design that includes a bias voltage generation circuit and a target circuit, utilizing transistors and capacitors to generate and supply bias voltages to tolerant elements, allowing operation at higher power voltages within the core region, with the bias circuit integrated adjacent to the core circuit to minimize leakage and improve integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If elements with higher breakdown voltages are arranged to implement a circuit operating with high power voltage, then the circuit can operate at higher voltage levels, but the degree of integration decreases and the number of process operations increases

Engineering Contradiction:
Improvebreakdown voltageVSAvoiddegree of integration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the electrical parameters of standard elements by applying bias voltages to modify their breakdown characteristics. By controlling the gate voltage of MOS transistors, the breakdown voltage can be dynamically adjusted, allowing standard low-voltage elements to safely operate in high-voltage circuits without requiring specialized high-voltage fabrication processes.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces bias voltage circuits as intermediary components that mediate between the high power voltage and the standard elements. These bias circuits generate controlled voltage levels applied to element gates, effectively acting as a buffer that enables high-voltage operation while protecting standard elements from direct exposure to damaging high voltages.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If elements with higher breakdown voltages are arranged to implement a circuit operating with high power voltage, then the circuit can operate at higher voltage levels, but the number of process operations increases

Engineering Contradiction:
Improvebreakdown voltageVSAvoidnumber of process operations
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent utilizes parameter changes in the electrical characteristics of standard MOS transistors through bias voltage application, eliminating the need for separate high-voltage fabrication processes. This approach allows the same manufacturing process line to produce both standard and high-voltage capable elements, significantly reducing the number of process operations required.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent makes standard MOS transistors multi-functional by enabling them to operate in both normal low-voltage modes and high-voltage modes through bias voltage control. This universality allows a single element design and fabrication process to serve multiple voltage requirements, eliminating the need for separate high-voltage element fabrication processes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If the bias circuit is integrated adjacent to the core circuit, then the degree of integration is improved, but leakage characteristics may worsen

Engineering Contradiction:
Improvedegree of integrationVSAvoidleakage current
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The integrated bias circuit acts as an intermediary that is strategically positioned adjacent to the core circuit. This location allows the bias circuit to provide necessary voltage control while maintaining sufficient physical separation to minimize leakage current paths. The bias circuit generates and distributes controlled voltage levels to core elements without creating significant leakage issues.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies local quality by integrating the bias circuit in a specific location adjacent to the core circuit rather than uniformly distributing it. This localized integration optimizes the balance between integration density and leakage management, placing the bias circuit where it can most effectively serve the core circuit while maintaining appropriate spacing to control leakage currents.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design enables stable operation at higher power voltages with reduced leakage and improved integration by using bias circuits integrated within the core region, stabilizing voltage levels and preventing element damage, thus enhancing the semiconductor device's performance.

Implementation Method 1

a plurality of capacitors connected to some transistors among the plurality of transistors, wherein each of the plurality of capacitors is connected in parallel with a corresponding transistor of the some transistors

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS20250323642A1Semiconductor device
Publication Date: 2025.10.16 SAMSUNG ELECTRONICS CO LTD
  • US20250323642A1 patent drawing
  • US20250323642A1 patent drawing
  • US20250323642A1 patent drawing

AI summary

A semiconductor device includes a bias voltage generation circuit generating a plurality of bias voltages. The bias voltage generation circuit includes a plurality of transistors connected in series between a first power node supplying a first power voltage and a reference node supplying a reference voltage, lower than the first power voltage, a plurality of capacitors connected to some transistors among the plurality of transistors, wherein each of the plurality of capacitors is connected in parallel with a corresponding transistor of the some transistors, and a turn-on circuit configured to supply a turn-on voltage to a gate of a first transistor among the plurality of transistors. Each of the turn-on circuit and the first transistor is directly connected to the first power node. Each of the plurality of transistors has a gate and a drain, electrically connected to each other.