Bias Voltage Generation Circuit Phase Margin Compensation
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Solution Overview
Problem
The conventional bias voltage generation circuit in PLL systems suffers from a decreased phase margin due to the pole created by the N-bias voltage generation circuit, leading to instability and jitter peaking caused by input clock noise and power noise, which deteriorates the jitter characteristic.
Innovation Solution
A bias voltage generation circuit that includes a bias unit configured to control current in response to a bandwidth control signal, an amplification unit to differentially amplify the input signal based on the controlled current, and an output unit to output the bias voltage, allowing for control of the bandwidth by adjusting the capacitance of the capacitor CLOAD, thereby improving phase margin and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bias voltage generation circuit is used in a PLL system, then the circuit can generate the necessary bias voltage for MOS transistors, but the phase margin decreases due to the pole created by the N-bias voltage generation circuit
Solution Approach 1:
The patent introduces a compensating capacitor Cc as an intermediary element that counteracts the harmful pole effect. This capacitor acts as a mediator between the bias voltage generation circuit and the PLL system, providing phase compensation to improve the phase margin without requiring a complete redesign of the bias generation circuitry.
Solution Approach 2:
The patent implements a feedback mechanism where the compensating capacitor Cc is connected to the output node of the bias voltage generation circuit. This feedback path allows the circuit to sense and compensate for the phase degradation caused by the pole, thereby improving the overall phase margin of the PLL system.
2Reliability
If the N-bias voltage generation circuit operates with conventional parameters, then it can provide bias voltage, but jitter peaking occurs due to input clock noise and power noise
Solution Approach 1:
The compensating capacitor Cc serves as an intermediary that filters and attenuates noise signals before they can propagate through the bias voltage generation circuit. By positioning this capacitor at the output node, it acts as a noise barrier that reduces the impact of input clock noise and power noise on the PLL system.
Solution Approach 2:
The patent applies beforehand cushioning by pre-configuring the compensating capacitor Cc to counteract noise effects before they can significantly degrade the jitter characteristic. This proactive noise compensation mechanism cushions the PLL system against the harmful effects of noise, preventing jitter peaking rather than correcting it after occurrence.
3Speed
If the bandwidth of the bias voltage generation circuit is increased to improve response, then the phase margin decreases and stability deteriorates
Solution Approach 1:
The patent employs parameter changes by introducing the compensating capacitor Cc with a specifically designed capacitance value. This parameter adjustment allows the circuit to achieve a favorable trade-off between bandwidth and phase margin, enabling the bias voltage generation circuit to operate at higher bandwidths without sacrificing stability.
Solution Approach 2:
The feedback path created by the compensating capacitor Cc provides phase compensation that counteracts the phase degradation associated with increased bandwidth. This feedback mechanism allows the circuit to maintain stability even when operating at higher bandwidths, effectively decoupling the bandwidth-stability trade-off.
Data Source
AI summary
Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.