Biased Branch Trace Cache for Smaller, More Predictable Fetch
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Solution Overview
Problem
Trace caches in traditional processor designs face challenges due to high power consumption and area usage, especially when branches unexpectedly exit the cache, which impedes their practical implementation.
Innovation Solution
Implementing a trace cache that caches only traces with internal control transfer instructions that meet certain stability criteria, such as being 'stable' based on historical execution bias, and using biased branch predictors to predict these instructions, thereby reducing the size of the trace cache and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a trace cache is implemented to improve instruction fetch bandwidth and reduce fetch power consumption, then performance is improved, but processor area and power consumption increase
Solution Approach 1:
The patent applies parameter changes by filtering traces based on the bias level of internal control transfer instructions. Only traces where internal branches meet a minimum bias threshold (e.g., 75% or 90% bias toward one direction) are admitted to the trace cache. This selective admission policy changes the composition parameter of cached traces, ensuring higher predictability and reducing the need for large cache capacity to handle unpredictable branches, thereby reducing processor area while maintaining high fetch bandwidth.
Solution Approach 2:
The patent applies local quality by differentiating between internal control transfer instructions based on their bias characteristics. Internal branches with high bias (stable behavior) are treated differently from those with low bias (unstable behavior). The trace cache selectively caches only those traces where internal branches exhibit sufficient bias, creating a localized quality filter that improves overall cache efficiency and reduces the area required to achieve the same performance level.
2Productivity
If a trace cache caches traces with internal control transfer instructions to improve performance, then instruction fetch efficiency is improved, but unexpected branch exits increase power consumption and reduce reliability
Solution Approach 1:
The patent changes the admission parameter for trace cache by enforcing a minimum bias threshold on internal control transfer instructions. Traces are only admitted if their internal branches meet the bias criterion (e.g., 75% or 90% bias). This parameter change ensures that cached traces have predictable branch behavior, significantly reducing unexpected branch exits and improving branch prediction accuracy while maintaining high instruction fetch efficiency.
Solution Approach 2:
The patent implements feedback through bias tracking mechanisms that monitor the execution behavior of control transfer instructions. The system tracks the actual bias of branches and uses this feedback to determine whether traces should be admitted to or evicted from the trace cache. This feedback loop ensures that only traces with reliably predictable branch behavior are cached, improving reliability while maintaining performance.
3Productivity
If the trace cache size is increased to handle more traces, then instruction fetch bandwidth is improved, but power consumption and area usage increase
Solution Approach 1:
The patent applies parameter changes by selectively admitting traces based on internal branch bias characteristics. Instead of caching all possible traces, the system filters for traces where internal branches meet a minimum bias threshold. This parameter-based selection improves the hit rate and instruction fetch bandwidth from a smaller cache, reducing the power consumption associated with larger cache structures while maintaining high productivity.
4Adaptability or versatility
If traditional trace cache implementations are used without bias filtering, then trace cache coverage is maximized, but device complexity and power consumption increase
Solution Approach 1:
The patent applies parameter changes by introducing bias threshold filtering as a selection criterion for trace admission. This parameter change simplifies the control logic by providing a clear, quantifiable rule for trace admission decisions. Instead of complex dynamic analysis, the system uses a straightforward bias threshold check, reducing device complexity while maintaining adequate trace cache coverage for predictable workloads.
Data Source
AI summary
Disclosed techniques relate to trace cache circuitry configured to identify and cache traces that satisfy certain criteria. Prediction circuitry may track directions of executed control transfer instructions, including a first category of control transfer instructions that meet a first threshold bias level toward a given direction (which may be referred to as “stable”) and a second category of control transfer instructions that do not meet the first threshold bias level (which may be referred to as “unstable”). Trace cache circuitry may identify traces of instructions that satisfy a set of criteria, including: only control transfer instructions of the first category are allowed as internal control transfer instructions and a control transfer instruction in the second category is allowed only at an end of a given trace. Disclosed techniques may advantageously provide performance and power advantages of trace caching with reduced complexity, relative to certain traditional trace caches.