Biased Field Plate LDMOS Layout for Breakdown and RDS(on)
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Drain extended transistors in high voltage applications face challenges with non-uniform electric fields leading to sub-optimal breakdown voltage performance and increased on-state resistance due to the non-uniform electric field under the polysilicon field plate, which is addressed by increasing the lateral drift region length, inhibiting efforts to reduce circuit area and increase drain-source resistance.
Innovation Solution
A biased field plate is introduced over the drain extended transistor, with its position and bias voltage determined through simulation and model adjustment to enhance electric field uniformity and maintain low on-state resistance without increasing the drift region length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the lateral drift region length is increased to improve breakdown voltage performance, then the breakdown voltage is improved, but the on-state drain-source resistance increases and circuit area increases
Solution Approach 1:
The patent applies parameter changes by introducing a biased field plate with optimized position and bias voltage to modify the electric field distribution in the drift region. This allows achieving improved breakdown voltage performance without increasing the lateral drift region length, thus resolving the contradiction between reliability and area.
2Reliability
If the lateral drift region length is increased to improve breakdown voltage performance, then the breakdown voltage is improved, but the on-state drain-source resistance increases
Solution Approach 1:
The patent modifies the electric field distribution through a biased field plate, enabling improved breakdown voltage without increasing drift region length. This prevents the increase in on-state resistance that would result from a longer drift region, thus resolving the contradiction between reliability and manufacturing precision.
3Stability of the object's composition
If a polysilicon field plate is used to improve drift region charge balance, then the charge balance is improved, but a non-uniform electric field is created with peaks in the drift region
Solution Approach 1:
The patent introduces a biased field plate with optimized position and bias voltage to reshape the electric field distribution. This eliminates the electric field peaks created by conventional polysilicon field plates while maintaining drift region charge balance, thus resolving the contradiction between stability and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The biased field plate achieves improved off-state breakdown voltage performance and reduced on-state drain-source resistance by optimizing the electric field profile, maintaining small half pitch dimensions and enhancing transistor reliability.
Implementation Method 1
The non-uniform electric field reduces the breakdown voltage from an ideal value... The biased field plate achieves improved off-state breakdown voltage performance by optimizing the electric field profile
Implementation Method 2
The extended drain architecture has a lightly doped drift region that allows carrier depletion under drain reverse bias so that the drain can block current flow during high voltage operation
Data Source
AI summary
A method of fabricating a semiconductor device includes creating a device model of a drain extended transistor with a biased field plate, simulating performance of the drain extended transistor using the device model, adjusting the device model based on the simulation to create an adjusted device model to improve a figure of merit, and creating a circuit model of the drain extended transistor based on the adjusted device model. A semiconductor device includes a drain extended transistor having a field relief dielectric layer over a drain drift region, and a biased field plate over the field relief dielectric layer where a position and bias voltage of the field plate are determined by adjusting a device model of the drain extended transistor based on simulated performance of the drain extended transistor using the device model.