Biased Bang-Bang Phase Detector for Data Eye Phase Lock
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional bang-bang phase detectors in clock and data recovery circuits face challenges in achieving precise phase convergence and low bit-error rates, particularly in serializer-deserializer communication channels, where they often settle at the median of jitter distribution rather than optimizing for desired bit-error rates.
Innovation Solution
A biased bang-bang phase detector is implemented, which generates phase up and phase down signals from data samples and transition samples, with a summing circuit providing weighted adjustments to bias the phase convergence to the inner corners of the receiver data eye, allowing lock at desired bit-error rates by controlling the ratio of two parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional bang-bang phase detector is used, then the circuit structure is simple, but the phase convergence accuracy is insufficient and it settles at the median of jitter distribution rather than achieving desired bit-error rates
Solution Approach 1:
The phase detector is divided into multiple parallel phase detector circuits, each generating phase up and phase down signals independently. These segmented detectors process different aspects of the phase error and their outputs are combined through a summing circuit, enabling more precise phase convergence while maintaining modular simplicity in each individual detector unit.
Solution Approach 2:
The invention introduces a bias parameter through the summing circuit that weights the phase up and phase down signals differently. By adjusting these weights, the system can shift the convergence point from the median to specific positions within the data eye, achieving desired bit-error rates. This parameter change transforms the fixed convergence behavior of conventional detectors into an adjustable system.
2Reliability
If the phase detector settles at the median of jitter distribution, then the circuit operation is stable, but the bit-error rate performance is insufficient for high-reliability communication
Solution Approach 1:
The summing circuit combines feedback from multiple phase detector circuits, each providing phase up and phase down signals based on their respective data samples and transition samples. This multi-path feedback mechanism enables the system to achieve more reliable phase locking by aggregating information from multiple detection paths, improving bit-error rate performance while maintaining stable operation.
3Measurement precision
If multiple phase detector circuits are used with weighted summing, then the phase convergence precision is improved, but the device complexity increases
Solution Approach 1:
Multiple phase detector circuits are merged through a summing circuit that combines their phase up and phase down signals. This merging approach allows the system to achieve higher detection precision by aggregating information from multiple parallel detectors while consolidating the complexity into a single integration point, rather than requiring complex individual detector units.
Data Source
AI summary
An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.