Biased Synchronizer Flip-Flop for Low-Latency Clock Crossing
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Solution Overview
Problem
Existing synchronizer flip-flops, including D flip-flops, suffer from latency issues that affect the speed at which they can stabilize and store data as states of the data input and clock signal change.
Innovation Solution
The implementation of a synchronizer flip-flop circuit that includes two or more inverters coupled in series or in a multi-stage scheme, with each inverter having transistors fed by a bias voltage provided by a diode-connected transistor, which reduces the threshold voltage of the transistors and increases data latching efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of inverter stages is increased to increase mean time between failure, then reliability is improved, but area and cost increase
Solution Approach 1:
The patent changes the electrical parameters of the inverter stages by introducing bias voltages that modify the threshold voltages of transistors. This allows achieving improved reliability through parameter optimization rather than increasing the number of stages, thereby avoiding additional area consumption
Solution Approach 2:
The patent introduces dynamically adjustable bias voltages to the inverter stages, allowing the threshold voltages to be optimized for different operating conditions. This dynamic adjustment enables reliable operation with fewer stages by adapting the electrical characteristics to maximize performance
2Reliability
If the number of inverter stages is increased to increase mean time between failure, then reliability is improved, but device complexity increases
Solution Approach 1:
Instead of adding more inverter stages, the patent modifies the electrical parameters of existing stages through bias voltage application. This approach achieves enhanced reliability while maintaining the same structural complexity, avoiding the need for additional components
3Speed
If latency is reduced by decreasing the number of inverter stages, then speed is improved, but reliability may deteriorate
Solution Approach 1:
The patent applies bias voltages to adjust threshold voltages of transistors in the inverter stages, optimizing the switching characteristics. This enables faster operation with fewer stages while compensating for the reduced redundancy through improved electrical parameter optimization
Solution Approach 2:
By introducing dynamically controllable bias voltages, the patent enables the inverter stages to operate at optimized speeds while maintaining reliability. The dynamic adjustment allows the circuit to achieve fast switching with fewer stages by adapting electrical characteristics in real-time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces latency within the flip-flop circuit and overall digital circuit, while also reducing design cost by avoiding the need for large numbers of inverters and using internal power supplies to generate bias voltages.
Implementation Method 1
a first diode-connected transistor coupled to a body of each transistor of the first set of transistors... which reduces the threshold voltage of the transistors
Data Source
AI summary
Embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. In an example, a synchronizer flip-flop circuit is provided. The synchronizer flip-flop circuit includes a first latch sub-circuit coupled to receive an input and a second latch sub-circuit coupled to the first latch sub-circuit. The first latch sub-circuit includes a first group of inverters, a first diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a first bias voltage to each inverter of the first group of inverters, and a second diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a second bias voltage to each inverter of the first group of inverters.