Biasing Dummy Global Bitlines Without Metal Contacts
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Solution Overview
Problem
Conventional memory devices face challenges in efficiently biasing dummy global bitlines without using metal contacts, which can complicate the layout and increase the number of dummy global bitlines, making it difficult to reduce chip size while maintaining test coverage.
Innovation Solution
The memory device employs a configuration where the land pattern layer (LP_DAM) of the memory cell region is connected to the bottom poly layer (BP) of the sense amplifier region, allowing biasing of dummy global bitlines without metal contacts, thereby reducing the number of dummy global bitlines and simplifying the layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy global bitlines are biased using metal contacts, then the biasing function is achieved, but the layout becomes complicated and chip size increases
Solution Approach 1:
The patent extracts the metal contact layer from the biasing structure, replacing it with a direct connection between the land pattern layer and bottom poly layer. This removes the unnecessary metal contact component while maintaining the biasing function, thereby reducing layout complexity and chip size.
Solution Approach 2:
The patent merges the land pattern layer with the bottom poly layer to create a direct electrical connection for biasing the dummy global bitline. This consolidation eliminates the need for separate metal contact structures, simplifying the overall layout and reducing the number of required dummy global bitlines.
2Reliability
If the number of dummy global bitlines is increased, then test coverage is improved, but chip size and layout complexity increase
Solution Approach 1:
The land pattern layer is designed to serve multiple functions: it acts as both the ground structure and the biasing connection for dummy global bitlines. This multi-functionality reduces the need for separate dedicated biasing structures, thereby reducing the number of dummy global bitlines required while maintaining test coverage.
3Reliability
If metal contacts are used for biasing, then electrical connection is established, but the layout becomes more complex
Solution Approach 1:
The patent removes the metal contact layer from the biasing path, establishing a direct electrical connection between the land pattern layer and bottom poly layer. This extraction of the metal contact component simplifies the layout while maintaining reliable electrical connection for biasing.
Data Source
AI summary
A memory device includes first global bitlines adjacent to a first edge portion of a memory cell region, second global bitlines adjacent to a second edge portion of the memory cell region; dummy global bitlines in a central portion of the memory cell region, and a bitline sense amplifier in a sense amplifier region and connected to the first global bitlines, the second global bitlines, and the dummy global bitlines A first layer of the memory cell region is connected to a second layer of the sense amplifier region and is configured to apply a bias voltage to each of the dummy global bitlines.