LDPC Bit-Group Interleaving for 1024-Symbol Burst Error Spreading

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Solution Overview

Problem

Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.

Innovation Solution

A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 4/15, using 1024-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis, with a specific permutation order, suitable for next-generation broadcasting systems like ATSC 3.0.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation

Engineering Contradiction:
Improvesystem performanceVSAvoidinterleaver design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the bit interleaver into multiple functional components: a parallel factor determination unit, a bit group division unit, and a permutation application unit. This segmentation allows the complex interleaving operation to be broken down into manageable steps, improving reliability while controlling design complexity through modular architecture

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by pre-defining specific permutation orders optimized for different modulation schemes and code rates. These permutation sequences are determined in advance and stored for direct application, eliminating the need for complex real-time calculations and ensuring optimal error distribution performance

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the bit interleaver is optimized for specific modulation order and code rate parameters, then performance improves, but the adaptability to different broadcasting standards decreases

Engineering Contradiction:
Improveerror correction performanceVSAvoidcompatibility with broadcasting standards
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamics by making the interleaver configuration adaptable to different broadcasting standards and parameters. The system can dynamically select appropriate permutation orders and bit group sizes based on the specific modulation scheme and code rate being used, maintaining optimal performance across diverse applications including ATSC 3.0, DVB-T2, and DVB-NGH

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies parameter changes by allowing the interleaver to adjust its operating parameters (such as bit group size, permutation order, and parallel factor) based on the specific broadcasting standard and modulation scheme. This enables the same interleaver structure to be optimized for different code rates and modulation orders without sacrificing adaptability

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10447305B2Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and 1024-symbol mapping, and bit interleaving method using same
Publication Date: 2019.10.15 ELECTRONICS & TELECOMM RES INST
  • US10447305B2 patent drawing
  • US10447305B2 patent drawing
  • US10447305B2 patent drawing

AI summary

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.