BICM-ID Receiver Memory Layout for Faster 64APSK Iterative Decoding
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Solution Overview
Problem
Current implementations of bit-interleaved coded modulation with iterative decoding (BICM-ID) face complexity and processing time penalties due to hardware requirements and memory access limitations, especially for higher modulation types like 64APSK, which affects system performance and capacity in communication systems.
Innovation Solution
The use of split channel RAMs for on-the-fly deinterleaving and interleaving, along with parallel processing of soft decision calculations, reduces processing time and improves information exchange between the demapper and decoder, enabling efficient operation across various modulation types without increasing hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BICM-ID with iterative decoding is implemented, then system performance and channel capacity are improved, but hardware complexity and processing time increase
Solution Approach 1:
The channel RAM is divided into multiple sub-memories (first sub-memories and second sub-memories) that are independently accessible. This segmentation allows parallel processing of extrinsic information for multiple code bits simultaneously, reducing the overall processing time and hardware complexity while maintaining the iterative decoding functionality
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing memory access patterns across multiple sub-memories. Instead of sequential access to a single memory structure, the system accesses multiple sub-memories in parallel, effectively adding a temporal dimension to the processing architecture that reduces iteration time without increasing sequential complexity
2Productivity
If higher modulation types like 64APSK are used, then channel capacity increases, but processing time and hardware requirements increase
Solution Approach 1:
By segmenting the channel RAM into multiple sub-memories, the system can process the larger number of code bits associated with higher modulation types (like 64APSK with 6 bits per symbol) in parallel. Each sub-memory handles a portion of the extrinsic information simultaneously, preventing processing time from increasing linearly with modulation order
Solution Approach 2:
The patent changes the memory organization parameter from a single monolithic structure to multiple sub-memories with specific access patterns. This parameter change allows the system to efficiently handle variable modulation types by adjusting which sub-memories are accessed and how many parallel operations are performed, scaling with modulation order without proportional time penalty
3Loss of information
If iterative decoding is performed, then information exchange between demapper and decoder improves, but memory access time increases
Solution Approach 1:
The extrinsic information exchange is segmented across multiple sub-memories, allowing the demapper and decoder to access different portions of the information simultaneously. This parallel access structure maintains the quality of iterative information exchange while reducing the total memory access time by eliminating sequential bottlenecks
Solution Approach 2:
The segmented memory structure enables continuous useful action during iterative decoding by allowing overlapping operations. While one sub-memory is being read, another can be written to, maintaining continuous information flow between iterations without idle wait states that would increase access time
Data Source
AI summary
The disclosure relates to bit-interleaved coded modulation with iterative decoding. In some implementations, a receiver comprises: a first memory including multiple first sub-memories; a decoder configured to perform first operations comprising: calculating, first extrinsic information of multiple code bits associated with multiple received symbols; and a demapper configured to perform second operations comprising: calculating soft decision information of the code bits; calculating, based on the soft decision information and the first extrinsic information, second extrinsic information of the code bits; and writing the second extrinsic information of the code bits into the first memory such that, for each received symbol, each sub-memory of the first sub-memories respectively stores the second extrinsic information associated with a respective one of the code bits corresponding to the received symbol.