LDPC Bit Interleaving for 256-Symbol Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation unless burst errors in digital broadcast channels are appropriately distributed, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 2/15, using a processor to generate interleaved codewords on a bit group basis and a modulator for 256-symbol mapping, with a specific permutation order to effectively distribute burst errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bit interleaver is used to distribute burst errors in BICM systems, then reliability is improved, but device complexity increases due to the need for optimized interleaver design matching specific modulation order and error correction code parameters
Solution Approach 1:
The patent applies parameter changes by designing the interleaver with specific parameters matched to the LDPC code (length 64800, code rate 2/15) and modulation scheme (256-QAM). The interleaver uses a permutation pattern optimized for these specific parameters, transforming the generic interleaver into a specialized component that achieves optimal error distribution for the given system configuration.
Solution Approach 2:
The patent segments the 64800-bit LDPC codeword into multiple blocks of 360 bits each (180 blocks total). This segmentation allows the interleaver to process and distribute errors across distinct blocks, improving the effectiveness of error distribution while managing complexity through modular processing of smaller units rather than handling the entire codeword as a single unit.
2Manufacturing precision
If the interleaver is optimized for specific LDPC code parameters and modulation order, then manufacturing precision is improved, but adaptability deteriorates
Solution Approach 1:
The patent implements parameter changes by configuring the interleaver with specific parameters (codeword length 64800, block size 360, number of blocks 180, permutation pattern) that are precisely matched to the LDPC code and modulation scheme. This optimization achieves high manufacturing precision for the target system while the patent acknowledges the trade-off with adaptability to other parameters.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.