BiCMOS Clock Driver Charge-Shuffling for Low Phase Noise
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Solution Overview
Problem
Existing clock driver circuits face challenges in achieving low phase noise and high speed while translating low-phase noise signals from ECL or small sinusoid waveforms to CMOS logic levels, often resulting in poor phase noise performance, limited speed, or excessive power consumption.
Innovation Solution
A BiCMOS clock driver circuit that actively drives the first MOSFET gates both up and down, using BJT emitter followers and MOSFET switches to shuffle charge stored on dummy MOSFET gates, reducing the dependence on current source noise and improving phase noise performance by employing additional MOSFETs as switches and capacitors to manage voltage swings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CMOS logic circuits are used to achieve low phase noise, then larger signal swings can overcome noise, but the inherent noise in MOSFET devices increases phase noise
Solution Approach 1:
The patent employs a BiCMOS circuit that combines Bipolar Junction Transistors (BJTs) and Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) to leverage the low noise characteristics of BJTs and the high input impedance of MOSFETs, achieving low phase noise while maintaining CMOS compatibility
Solution Approach 2:
The patent introduces an intermediate stage with BJTs that acts as a buffer between the low-phase noise signal source and the CMOS logic circuitry, isolating the noise-sensitive CMOS devices from the signal source and preventing noise degradation
2Measurement precision
If prior conversion circuits are used to translate low-phase noise signals to CMOS logic levels, then signal level translation is achieved, but phase noise performance degrades due to capacitive loading and slew-rate limitations
Solution Approach 1:
The patent employs dynamic sizing of transistors in the conversion circuit, where the width and length of MOSFET channels are optimized to provide sufficient drive current for fast switching while maintaining low capacitive loading on the signal path, thereby achieving both high speed and low phase noise
Solution Approach 2:
The patent optimizes key circuit parameters including bias current levels, transistor aspect ratios, and load capacitance values to achieve the optimal trade-off between switching speed and phase noise performance, allowing the circuit to operate at high speeds without degrading phase noise
3Measurement precision
If prior conversion circuits are used to translate low-phase noise signals to CMOS logic levels, then signal level translation is achieved, but excessive power is consumed to drive MOSFET gates
Solution Approach 1:
The patent optimizes the bias current and transistor sizing parameters to minimize power consumption while maintaining adequate drive capability for the MOSFET gates, achieving a balance between power efficiency and signal integrity
Solution Approach 2:
The patent uses a differential pair configuration where the signal is replicated across symmetric transistor paths, allowing the use of smaller individual transistors with lower gate capacitance, thereby reducing the total power required to drive the gates while maintaining signal fidelity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit achieves reduced phase noise and improved speed with minimal increase in bias current levels, providing effective phase noise performance and efficient operation.
Implementation Method 1
MOSFET switches to shuffle charge stored on dummy MOSFET gates
Data Source
AI summary
System and method for a clock driver. An input taking circuit is used for receiving small-signal logic inputs. A voltage follower circuit is coupled to the input taking circuit and used to generate a set of voltage follower outputs. An output circuit is coupled to the voltage follower circuit to receive the set of voltage follower outputs as inputs and generate output signals. The voltage follower circuit is coupled to a switching circuit, that is connected to the set of voltage follower outputs and is deployed for reducing the phase noise level of the output signals.