BiCMOS Clock Driver Gate Control for Reduced Phase Noise
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Solution Overview
Problem
Existing clock driver circuits face challenges in achieving low phase noise and high speed while maintaining low power consumption, as they often suffer from increased noise and timing uncertainties due to limitations in rail-to-rail signal swings and quiescent current levels, particularly when translating low-phase noise signals from ECL to CMOS logic levels.
Innovation Solution
The proposed BiCMOS clock driver circuit actively drives MOSFET gates both up and down, using BJT emitter followers and MOSFET switches to manage charge storage, thereby reducing phase noise by minimizing dependence on current source noise and improving signal-to-noise ratios without increasing bias current levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CMOS logic circuits are used to achieve low phase noise, then phase noise performance is improved, but speed and power consumption deteriorate due to higher inherent noise in MOSFET devices and limited signal swing
Solution Approach 1:
The patent combines BJT and CMOS technologies in a BiCMOS circuit architecture. The BJT differential pair provides low-noise signal processing while the CMOS circuit provides rail-to-rail signal swing capability. This merging allows the circuit to achieve both low phase noise and high speed performance that neither technology could achieve alone.
Solution Approach 2:
The patent uses a composite transistor architecture combining bipolar and MOSFET devices. The BJT input stage processes the low-level signal with high precision, while the CMOS output stage delivers full swing voltage levels. This composite approach creates a circuit that leverages the strengths of both device types to resolve the speed-phase noise tradeoff.
2Measurement precision
If rail-to-rail CMOS signal levels are used to overcome inherent noise, then signal-to-noise ratio is improved, but power consumption increases due to the need for high current levels
Solution Approach 1:
The patent segments the signal processing function into two distinct stages: a BJT differential pair stage that processes the input signal at low current levels with high precision, and a CMOS output stage that converts to rail-to-rail levels. This segmentation allows each stage to operate at optimal current levels, achieving high signal-to-noise ratio without requiring high power consumption throughout the entire circuit.
Solution Approach 2:
The patent changes the operating parameters between stages: the BJT stage operates with small signal swings and low current to minimize noise, while the CMOS stage operates with large voltage swings and controlled current to achieve rail-to-rail output. This parameter transformation allows the circuit to achieve high signal-to-noise ratio at the output without consuming excessive power throughout the circuit.
3Measurement precision
If BJT differential pairs are used to process low-level signals, then phase noise is reduced, but speed is limited due to quiescent current levels and capacitance
Solution Approach 1:
The patent introduces a CMOS buffer stage as an intermediary between the BJT differential pair and the final output. This intermediary stage converts the low-level BJT output signal to rail-to-rail CMOS levels, providing both voltage amplification and isolation. This allows the BJT stage to operate at low current for low noise while the CMOS stage provides the speed and drive capability needed for high operational frequency.
4Stress or pressure
If current sources are used to charge capacitance in BJT circuits, then voltage swing is achieved, but noise is introduced that degrades phase noise proportionally with current noise level
Solution Approach 1:
The patent extracts the noise-sensitive current charging function from the BJT input stage and relocates it to the CMOS output stage. The BJT differential pair is used only for low-noise signal processing, while the CMOS circuit handles the voltage swing generation and current charging functions. This separation removes the noise-degrading current charging action from the sensitive input stage, preserving phase noise performance while still achieving the necessary voltage swing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances phase noise performance and operational speed while maintaining low power consumption by actively managing gate voltages and reducing noise contributions from current sources, resulting in improved signal integrity and reduced timing uncertainties.
Implementation Method 1
BJT emitter followers and MOSFET switches to manage charge storage
Implementation Method 2
BJT emitter followers and MOSFET switches to manage charge storage
Data Source
AI summary
System and method for a clock driver. An input taking circuit is used for receiving small-signal logic inputs. A voltage follower circuit is coupled to the input taking circuit and used to generate a set of voltage follower outputs. An output circuit is coupled to the voltage follower circuit to receive the set of voltage follower outputs as inputs and generate output signals. The voltage follower circuit is coupled to a switching circuit, that is connected to the set of voltage follower outputs and is deployed for reducing the phase noise level of the output signals.