BiCMOS Gate Driver Resynchronization for Fast Class-S RF-PA Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing gate driver circuits for digital Class-S RF-PAs face challenges with high power dissipation, instability when driving capacitive loads, and breakdown limitations, particularly in achieving fast gate voltage rise times necessary for efficient switching in wireless communication systems.
Innovation Solution
A resynchronizing push-pull drive circuit employing cascoded CMOS complementary gate drivers and Vernier skew control to generate high-slew-rate, large-swing quasi-digital signals, capable of driving significant gate capacitance with improved stability and power consumption characteristics, using a combination of bipolar transistor current switches and cascoded CMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional medium/narrow bandwidth RF matching techniques are used for gate driving, then the circuit design is simple, but the gate voltage rise time is too slow to achieve efficient switching
Solution Approach 1:
The gate driver is segmented into multiple functional blocks: a current steering long-tailed pair for differential signal generation, emitter follower buffers for impedance matching and current amplification, and RF matching networks for optimal power transfer. Each segment performs a specific function to collectively achieve fast rise times while managing complexity.
Solution Approach 2:
Emitter follower buffers are introduced as intermediary stages between the current steering pair and the gate electrodes. These buffers act as mediators that provide current amplification and impedance transformation, enabling the driver to overcome the capacitive load of the gate while maintaining fast switching speeds.
2Speed
If a current-steering long-tailed pair with low-valued collector/drain loads is used to drive the gates directly, then the gate voltage rise time is fast, but power dissipation is high
Solution Approach 1:
Emitter follower buffers are inserted as intermediary stages between the current steering pair and the gate electrodes. These buffers provide current amplification with lower power consumption compared to direct driving, while maintaining the fast rise times generated by the current steering pair.
Solution Approach 2:
The circuit transforms the current output from the long-tailed pair into voltage swings at the gate electrodes through the emitter followers and RF matching networks. This parameter transformation allows the use of lower current values in the steering pair, reducing power dissipation while maintaining fast voltage rise times at the gates.
3Power
If complementary class-AB type emitter followers in a totem-pole arrangement are used for gate driving, then the circuit provides current amplification, but the circuit exhibits instabilities when driving capacitive loads
Solution Approach 1:
The gate driver is segmented into a current steering long-tailed pair for differential signal generation and emitter follower buffers for current amplification. This segmentation separates the functions of signal generation and current buffering, avoiding the instability issues of totem-pole emitter followers while maintaining current amplification capability.
Solution Approach 2:
The circuit incorporates feedback mechanisms through the differential configuration of the long-tailed pair and the use of complementary emitter followers. The differential structure provides inherent stability by rejecting common-mode disturbances, while the feedback paths in the emitter followers ensure stable operation when driving the capacitive gate loads.
4Ease of manufacture
If high-speed CMOS output buffers are used for gate driving, then the circuit integrates well with CMOS technology, but the transistors are subject to breakdown limitations due to thin-oxide narrow-gate length
Solution Approach 1:
The circuit uses a current steering long-tailed pair with emitter follower buffers as an intermediary stage between the CMOS logic and the gate electrodes. This intermediary structure allows the use of standard CMOS transistors without subjecting them to high voltage stress, avoiding breakdown issues while maintaining good CMOS integration.
Solution Approach 2:
The circuit transforms the voltage swings from standard CMOS levels to the higher voltage swings required at the gate electrodes through the emitter followers and RF matching networks. This parameter transformation allows standard CMOS transistors to operate within their safe voltage ranges while still driving the gates effectively.
Data Source
AI summary
The invention may be embodied in a resynchronizing, push-pull drive circuit for driving the gate electrodes of a digital Class-S Radio Frequency Power Amplifier (RF-PA). A binary bitstream received from a bitstream generator, such as a sigma-delta modulator, Viterbi-based optimal-bit-pattern modulator sigma-delta, or other suitable modulator, is resynchronized to a low-jitter master clock, then converted to fast-rise, high-swing complementary digital signals to drive the gates of the Class-S RF-PA. The drive circuit provides a high slew-rate, large-swing, quasi-digital gate drive circuit to drive the significant gate capacitance of the RF-PA with sufficient rise times. A combination of bipolar transistor current switches and cascoded CMOS devices is employed to attain requisite performance. For example, the driving circuit is well suited for use with Class-S RF-PAs used in wireless communication systems.