BiCS NAND Structure With Reverse VT States for Data Retention
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Solution Overview
Problem
NAND flash memory devices face challenges such as increased neighboring word line to word line interference and reduced data retention over program/erase cycles due to excessive hole injection during memory operations, leading to degradation of tunneling dielectric layers and reduced reliability.
Innovation Solution
The solution involves reversing programmed data states in non-volatile memory devices, where the erased state corresponds to the highest threshold voltage distribution, and utilizing direct poly-channel contacts for bit and source lines to reduce excessive hole injection, along with setting drain-side select gate threshold voltages to negative levels to minimize leakage currents in unselected NAND strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional programming operations are used to store data in NAND flash memory, then data capacity is achieved, but excessive hole injection occurs causing degradation of tunneling dielectric layers and reduced data retention
Solution Approach 1:
The patent inverts the conventional data state assignment by reversing the threshold voltage ranges for programmed data states. Instead of conventional ascending threshold voltages for data states, the patent uses descending threshold voltages where higher-order data states correspond to lower threshold voltages. This inversion reduces hole injection into the tunneling dielectric layer during programming operations, thereby improving data retention and reliability while maintaining data capacity.
2Ease of manufacture
If process geometries are shrunk to reduce cost per bit, then manufacturing cost is reduced, but neighboring word line to word line interference increases
Solution Approach 1:
The patent changes the parameter of threshold voltage distribution and data state assignment to mitigate word line interference. By reversing the threshold voltage ranges for programmed data states and optimizing the voltage levels, the patent reduces the electrical interference between neighboring word lines, enabling continued scaling to smaller geometries without proportionally increasing interference effects.
3Ease of operation
If conventional data state assignment is used, then programming operations are straightforward, but leakage currents in unselected NAND strings increase power consumption
Solution Approach 1:
The patent changes the threshold voltage parameter assignment for data states to reduce leakage currents. By assigning reversed threshold voltage ranges where higher-order data states have lower threshold voltages, the patent minimizes unwanted leakage currents in unselected NAND strings during read and verify operations, thereby reducing power consumption while maintaining programming operability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of memory cell transistors with threshold voltages below a negative threshold voltage, minimizing hole injection and enhancing data retention, while also reducing power consumption and battery degradation by minimizing leakage currents through unselected NAND strings.
Implementation Method 1
The amount of charge on the floating gate is typically controlled using Fowler-Nordheim (F-N) tunneling or hot-electron injection.
Implementation Method 2
The amount of charge on the floating gate is typically controlled using Fowler-Nordheim (F-N) tunneling or hot-electron injection.
Data Source
AI summary
Systems and methods for improving the reliability of non-volatile memory by reducing the number of memory cell transistors that experience excessive hole injection are described. The excessive hole injection may occur when the threshold voltage for a memory cell transistor is being set below a particular negative threshold voltage. To reduce the number of memory cell transistors with threshold voltages less than the particular negative threshold voltage, the programmed data states of the memory cell transistors may be reversed such that the erased state comprises the highest data state corresponding with the highest threshold voltage distribution. To facilitate programming of the memory cell transistors with reversed programmed data states, a non-volatile memory device structure may be used in which the bit line connections to NAND strings comprise direct poly-channel contact to P+ silicon and the source line connections to the NAND strings comprise direct poly-channel contact to N+ silicon.