Bi-directional Buck ESD Circuit for I/O Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor components in integrated circuits shrink, they become more susceptible to damage from electrostatic discharge (ESD) due to reduced breakage voltages, necessitating an effective ESD protection mechanism to prevent damage during manufacturing and operation.
Innovation Solution
An ESD circuit is designed with a bi-directional buck circuit, a triggering circuit, and a discharging circuit, which includes forward and reverse paths to manage ESD currents effectively, ensuring that ESD currents do not flow through the internal circuit, thereby protecting it from damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If semiconductor component sizes are decreased to increase operating speed and integration level, then operating speed and integration level are improved, but breakage voltage decreases making the components more susceptible to ESD damage
Solution Approach 1:
The patent introduces an ESD circuit as an intermediary component between the I/O pad and internal circuit. This ESD circuit includes a discharging circuit and triggering circuit that detect ESD events and provide a dedicated ESD current path, allowing ESD current to be diverted away from the internal circuit while maintaining normal operation of the scaled-down semiconductor components.
Solution Approach 2:
The ESD protection function is segmented into distinct circuit components: a bi-directional buck circuit with forward and reverse paths, a triggering circuit, and a discharging circuit. This segmentation allows each component to be optimized for its specific function while collectively providing comprehensive ESD protection for the scaled-down internal circuitry.
2Reliability
If conventional ESD protection circuits are added to protect internal circuits, then reliability against ESD damage is improved, but device complexity increases
Solution Approach 1:
The ESD circuit is designed to handle both positive and negative ESD zaps through its bi-directional buck circuit configuration. The forward path handles positive ESD events while the reverse path handles negative ESD events, allowing a single circuit design to provide universal protection against both polarities of ESD damage without requiring separate protection circuits for each case.
Solution Approach 2:
The patent combines the ESD detection, triggering, and current discharge functions into an integrated ESD circuit block that is connected between the I/O pad and internal circuit. This merging of functions reduces the overall complexity compared to having separate protection circuits for each function, while still providing comprehensive ESD protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ESD circuit effectively directs ESD currents away from the internal circuit, protecting it from damage during both negative and positive ESD zaps, even when the semiconductor components are operating near their breakage voltage limits, ensuring reliable operation.
Implementation Method 1
When the I/O pad receives a negative ESD zap, an ESD current flows from the first node to the I/O pad through the discharging circuit and the reverse path. When the I/O pad receives a positive ESD zap, the ESD current flows from the I/O pad to the first node through the forward path and the discharging circuit.
Data Source
AI summary
An ESD circuit is connected between an I/O pad and a first node. The ESD circuit includes a bi-directional buck circuit, a triggering circuit and a discharging circuit. The bi-directional buck circuit includes a forward path and a reverse path. The forward path and the reverse path are connected between the I/O pad and a second node. The triggering circuit is connected between the second node and the first node. The discharging circuit is connected between the second node and the first node, and connected with the triggering circuit. When the I/O pad receives negative ESD zap, the ESD current flows from the first node to the I/O pad through the discharging circuit and the reverse path. When the I/O pad receives positive ESD zap, the ESD current flows from the I/O pad to the first node through the forward path and the discharging circuit.