Bidirectional Buffer for Semiconductor Memory Data Bus

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Solution Overview

Problem

Conventional semiconductor memory devices face challenges in achieving high-speed data transfer rates due to increased wiring length, which leads to delays and higher consumption current, and struggle to selectively buffer data across multiple data buses connected to different areas of the memory cell array.

Innovation Solution

A semiconductor memory device configuration with a common data bus and individual data buses connected through bidirectional buffers, allowing for selective buffering of data between the common bus and individual buses, thereby reducing wiring length and circuit complexity, and enabling efficient data transfer across different areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the data bus is divided and a bidirectional buffer is inserted therebetween, then the wiring length of the data bus is shortened and data transfer rate is increased, but the number of wirings of the data bus connected through the bidirectional buffer cannot be reduced

Engineering Contradiction:
Improvedata transfer rateVSAvoidnumber of wirings
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory cell array is divided into a plurality of banks, and each bank is further divided into a plurality of areas. Individual data buses are assigned to connect specific banks to the common data bus, allowing selective buffering. This segmentation enables the bidirectional buffer to handle only the necessary data paths rather than all data bus connections, reducing the number of wirings that need to pass through the buffer while maintaining high-speed transfer capability.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If the storage capacity of semiconductor memory devices is increased, then the storage capacity is improved, but the number of wirings of the data bus is remarkably increased and chip area increases

Engineering Contradiction:
Improvestorage capacityVSAvoidchip area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The memory cell array is divided into multiple banks, and each bank is divided into multiple areas. This segmentation allows data from different banks to be transmitted through different individual data buses that connect to specific groups of areas in the bidirectional buffer. Consequently, the number of wirings required in the common data bus is reduced, leading to decreased chip area while maintaining increased storage capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A bidirectional buffer is introduced as an intermediary component between individual data buses and the common data bus. This buffer selectively transmits data from specific banks through specific paths, reducing the number of direct wiring connections required in the common data bus. The result is reduced chip area while supporting expanded storage capacity through efficient wiring utilization.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Length of stationary object

If conventional bidirectional buffer configurations are used, then wiring length is shortened, but it is difficult to selectively buffer transmission data through many data buses connected to different areas

Engineering Contradiction:
Improvewiring lengthVSAvoidselective buffering capability
Core Design Contradiction:
Length of stationary objectVSAdaptability or versatility

Solution Approach 1:

The bidirectional buffer is divided into a plurality of groups, with each group connected to receive data from a specific bank through an individual data bus. This segmentation enables selective buffering where data from different banks can be transmitted through different paths simultaneously. The buffer maintains short wiring lengths while providing the versatility to handle multiple data bus connections to different memory areas.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bidirectional buffer is configured to dynamically select which individual data bus data to transmit to the common data bus based on the source bank. This dynamic selection capability allows the system to adaptively route data from different banks through appropriate paths, providing selective buffering for many data buses connected to different areas while maintaining short wiring lengths.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8054699B2Semiconductor memory device having a double branching bidirectional buffer
Publication Date: 2011.11.08 LONGITUDE LICENSING LTD
  • US8054699B2 patent drawing
  • US8054699B2 patent drawing
  • US8054699B2 patent drawing

AI summary

A semiconductor memory device includes a memory cell array divided into a plurality of areas, a common data bus connected to an input/output circuit, a plurality of individual data buses connected to different areas of the memory cell array through different paths respectively, and a bidirectional buffer connected to the common data bus and the individual data buses. In the semiconductor memory device, the bidirectional buffers transmit data bidirectionally between the common data bus and a selected one of the individual data buses.