Bidirectional Buffer Segmentation for Memory Signal Coupling
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Solution Overview
Problem
As memory devices increase in capacity by adding more banks, the length of signal lines such as LDRW lines, digit lines, and word lines also increases, leading to higher capacitance and resistance, which slows down the operating speed of memory devices, creating a need for faster signal coupling methods without compromising capacity.
Innovation Solution
Implementing bidirectional buffers between segments of signal lines, such as LDRW lines, digit lines, and word lines, to facilitate quicker data transfer without the need for decoding circuitry, thereby reducing circuitry requirements and enhancing operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory banks is increased to enhance capacity, then the memory device capacity is improved, but the signal line length increases leading to higher capacitance and resistance which slows down operating speed
Solution Approach 1:
The patent divides long signal lines into multiple segments by inserting buffer circuits at intermediate points. This segmentation reduces the effective length of each signal line segment, thereby reducing capacitance and resistance in each segment while maintaining overall memory capacity through increased banks.
Solution Approach 2:
Buffer circuits are introduced as intermediary elements between memory banks and data terminals. These buffers act as signal regeneration points that reduce the electrical load and signal degradation caused by long signal lines, enabling both high capacity and high speed operation.
2Ease of operation
If conventional terminal data drivers are used to couple data through LDRW lines, then data transfer is achieved, but the circuitry complexity increases and operating speed is reduced
Solution Approach 1:
The patent employs bidirectional buffers that can operate in multiple modes (read mode and write mode) depending on control signals. This multi-functionality eliminates the need for separate terminal data drivers for reading and writing, reducing circuitry complexity while maintaining full data transfer capability in both directions.
Solution Approach 2:
Instead of using conventional terminal data drivers that require decoding circuitry, the patent inverts the approach by using bidirectional buffers controlled by simple read/write mode signals. This inversion simplifies the control logic and reduces overall circuitry complexity while achieving the same data coupling function.
Data Source
AI summary
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.