Bi-Directional Bus Buffering to Prevent Latching and Glitches
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Solution Overview
Problem
Existing bi-directional signal transmission systems, such as the I2C Bus system, face limitations in expanding capacity and distance due to capacitive load, leading to issues like latching and signal glitches, and fail to effectively buffer signals during bus contention, generating spurious signals.
Innovation Solution
A bi-directional signal transmission system with buffer circuitry that generates distinct logic levels for signal paths, using a diode-connected transistor and current sources to maintain optimal input threshold and output saturation voltages, independent of temperature, ensuring minimal variation and preventing latching and glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the bus capacitance is increased to expand the number of stations or distance, then the communication capacity and range are improved, but the maximum bus speed is limited and rise times increase causing difficulties
Solution Approach 1:
The patent introduces buffer circuits that segment the bus into multiple sections, each with controlled capacitance. The buffer circuits act as intermediate stages that isolate different segments, allowing the overall bus to extend beyond single-capacitance limits while maintaining signal integrity and speed requirements in each segment.
Solution Approach 2:
Buffer circuits are introduced as intermediary devices between distant or high-capacitance bus segments. These buffers actively drive signals and isolate capacitance effects, enabling extended communication range and station capacity without proportionally degrading signal rise times or maximum speed.
2Device complexity
If simple circuits are used to provide expanded capability, then device complexity is reduced, but latching and conditional stability problems occur
Solution Approach 1:
The buffer circuits incorporate feedback mechanisms that continuously monitor signal states and adjust output accordingly. This feedback ensures stable operation by preventing latching conditions where the circuit might incorrectly maintain a state, while still using relatively simple circuit topology that doesn't excessively increase device complexity.
3Reliability
If buffer circuits are used to prevent latching, then signal stability is improved, but the circuits fail to buffer signals effectively during bus contention generating spurious signals
Solution Approach 1:
The buffer circuits employ dynamic control mechanisms that adapt their buffering behavior based on real-time bus conditions. During bus contention, the circuits dynamically adjust their signal levels and timing to maintain stability without generating spurious signals, while under normal conditions they provide effective buffering to prevent latching.
Solution Approach 2:
The buffer circuits change their operating parameters (such as signal levels, timing characteristics, and drive strengths) based on detected bus conditions. This allows them to optimize performance for different scenarios - providing strong buffering when needed to prevent latching, and adjusting to avoid generating spurious signals during contention events.
Data Source
AI summary
A bi-directional signal transmission system including, a first bi-directional signal path having circuitry adapted to generate a logic high level on said first path, one or more first stations connected to the first bi-directional signal path adapted to monitor a logic level on said first path, and to generate a logic low level on said first path, an interface device operatively coupled to the first bi-directional signal path, said interface device having a first receive input also capable of functioning as an output capable of pulling the first path low; and a second bi-directional signal path coupled to a transmit output and a receive input on the buffered side of the interface device, said interface device includes a first means for generating on the first bi-directional signal path a medium logic level in response to a low level on the receive input on the buffered side, and a second means for generating on the transmit output on the buffered side, a low logic level in response to a low level on the first bi-directional signal path, otherwise generating a high level on the said transmit output, wherein the one or more first stations are adapted to detect the medium and the low levels on the first bi-directional signal path as LOW, and the high logic level on the first bi-directional signal path as HIGH, and wherein further the first means for generating the medium logic level on the first signal path includes an open collector transistor, the emitter of which is connected to VEE, with its collector pulling the first signal path low through a diode connected transistor.