Bidirectional Bus Clock Segmentation

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Solution Overview

Problem

Existing bidirectional data bus systems face challenges in efficiently transmitting data between modules with minimal power consumption and robustness against transmission delays and electromagnetic interference (EMI), particularly in applications requiring high data rates and low power modes.

Innovation Solution

A method involving a signal bus with a clock signal generated by a host module, where bit patterns are transmitted during specific half-periods of the clock signal, allowing for altered patterns to convey information, and enabling low power mode operation while maintaining robustness against EMI through differential signaling and synchronized clock phases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If bidirectional data transmission is implemented on a shared bus, then data communication capability is improved, but driver contention and signal interference occur

Engineering Contradiction:
Improvebidirectional data transmission capabilityVSAvoidsignal integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The bus transmission time is segmented into distinct half-periods, with even half-periods dedicated to one direction and odd half-periods to the other direction. This temporal segmentation eliminates driver contention by ensuring only one device drives the bus at any given time, while still enabling bidirectional communication capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system employs periodic alternating transmission directions synchronized with a clock signal. The bus operates in a periodic manner, switching between bidirectional modes at regular intervals defined by the clock period, which maintains signal integrity while providing bidirectional functionality.

Inventive Principle:
Principle #19Periodic action

2Speed

If high data rate transmission is implemented, then communication speed is improved, but power consumption increases

Engineering Contradiction:
Improvedata transmission rateVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The system uses periodic transmission bursts synchronized with clock cycles to achieve high data rates when needed, while allowing idle periods where transmission is suspended. This periodic operation enables the system to maintain high-speed capability while reducing average power consumption by not continuously operating at maximum speed.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The transmission system dynamically adjusts its operation between active high-speed transmission modes and low-power idle modes based on data availability and communication requirements. This dynamic operation allows the system to optimize the trade-off between data rate and power consumption in real-time.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10218535B2Low power bidirectional bus
Publication Date: 2019.02.26 CIRRUS LOGIC INC
  • US10218535B2 patent drawing
  • US10218535B2 patent drawing
  • US10218535B2 patent drawing

AI summary

A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.