Bidirectional Clock Sync Circuit With Selectable PLL Ranges
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Solution Overview
Problem
Network equipment synchronization is complicated by the need for multiple ports and varying synchronization signal types, making it challenging to verify and provide synchronization, especially with vendors offering single ports and different signal compatibility.
Innovation Solution
A bidirectional clock synchronization circuit with a phase locked loop (PLL) and transceiver, allowing for frequency range selection and operation as both input and output, integrated into a single port to facilitate easy synchronization and reduce equipment footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple ports are provided for clock input and output, then synchronization reliability is improved, but device complexity and footprint increase
Solution Approach 1:
The patent implements a bidirectional port that can function as both clock input and clock output, eliminating the need for separate dedicated input and output ports. The port's functionality is dynamically configured through control logic that switches its direction based on operational requirements, thereby maintaining synchronization reliability while reducing device complexity and footprint
2Adaptability or versatility
If multiple synchronization signal types are supported, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent employs a frequency-range selectable phase-locked loop (PLL) that can be configured to support multiple synchronization signal types by changing its operating parameters. The PLL's frequency range is adjusted according to the specific signal type required, enabling the device to adapt to different protocols (PTP, SyncE, etc.) without requiring separate dedicated circuits for each signal type, thus maintaining adaptability while controlling complexity
3Area of stationary object
If a single bidirectional port is used, then footprint is reduced, but measurement precision and verification capability deteriorate
Solution Approach 1:
The patent implements dynamic direction control for the bidirectional port, allowing it to switch between input and output modes as needed. This dynamic configuration enables the port to function as both clock input and clock output at different times, providing verification capability while maintaining a reduced footprint. The control logic manages the port's operational state to ensure proper synchronization verification can be performed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient synchronization using a single port, adaptable to various synchronization signals, reducing costs and simplifying the verification process, and supporting protocols like PTP and SyncE.
Implementation Method 1
The circuit includes a phase locked loop (PLL), having an output coupled to the unidirectional input of the transceiver, and having an input coupled to the unidirectional output of the transceiver, the phase locked loop selectable as to frequency range for the input or the output of the phase locked loop
Data Source
AI summary
A bidirectional clock synchronization circuit is provided. The circuit includes a bidirectional port having an input/output terminal and a transceiver, having a first interface with a unidirectional input and a unidirectional output, and a second interface with a bidirectional input/output coupled to the input/output terminal of the bidirectional port. The circuit includes a phase locked loop (PLL), having an output coupled to the unidirectional input of the transceiver, and having an input coupled to the unidirectional output of the transceiver, the phase locked loop selectable as to frequency range for the input or the output of the phase locked loop.