Shared DQ Line Signaling for Concurrent Data and Command Transfer

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Solution Overview

Problem

The data input/output efficiency of non-volatile memories connected to a shared channel is compromised due to the high transmission rate of data and the low transmission rate of commands, leading to reduced real-time processing capabilities as storage device capacity increases.

Innovation Solution

A method and storage device that simultaneously transmit data and embedded commands in both directions of a channel, using a memory controller with data and command logic circuits to manage the transmission over a single data signal line, thereby optimizing data input/output efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If serial transmission is used on shared channel, then device complexity is reduced, but productivity deteriorates

Engineering Contradiction:
Improvechannel structureVSAvoiddata input/output efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent enables continuous bidirectional communication on the shared DQ line by allowing data output and command input to occur simultaneously in different directions. This eliminates idle time where the line would otherwise be unused, maintaining continuous productive utilization of the communication channel while preserving the simple serial transmission structure.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS12210773B2Storage device for transmitting data having an embedded command in both directions of a shared channel, and a method of operating the storage device
Publication Date: 2025.01.28 SAMSUNG ELECTRONICS CO LTD
  • US12210773B2 patent drawing
  • US12210773B2 patent drawing
  • US12210773B2 patent drawing

AI summary

A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.