Bi-directional ESD Diode with Ultra-Low Capacitance
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Solution Overview
Problem
Conventional bi-directional ESD circuits with Zener and avalanche diodes consume a large amount of silicon real estate and have high capacitance, making them unsuitable for high-speed signal applications like USB 3.0 and HDMI 1.4.
Innovation Solution
A bi-directional ESD diode structure with ultra-low capacitance is achieved by incorporating a p− epitaxial layer between two n+ epitaxial layers, reducing silicon usage and capacitance while maintaining high breakdown voltages, through a method involving epitaxial growth and dopant concentration control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional combination of Zener and avalanche diodes is used, then the ESD circuit provides bidirectional protection, but the metal lead connecting the diodes consumes a large amount of silicon real estate
Solution Approach 1:
The patent merges the Zener diode and avalanche diode functions into a single integrated structure where shared regions (n-well, p-substrate) serve as common cathode and anode respectively. This eliminates the need for separate metal leads connecting the diodes, thereby reducing silicon real estate consumption while maintaining bidirectional ESD protection.
Solution Approach 2:
The shared n-well and p-substrate regions serve multiple functions simultaneously: they act as the cathode for both the Zener diode (when p+ region is anode) and the avalanche diode (when n+ region is anode), and also provide the breakdown voltage characteristics. This multi-functionality reduces the overall device area.
2Reliability
If a conventional combination of Zener and avalanche diodes is used, then the ESD circuit provides bidirectional protection, but the capacitance is high making it unsuitable for high-speed signal applications
Solution Approach 1:
The patent employs localized doping concentration variations within the shared regions to optimize performance. Specifically, the n-well has a first doping concentration and the p-substrate has a second doping concentration, with the junction between them engineered to provide both the required breakdown voltage and reduced capacitance. This local quality control enables high-speed signal capability while maintaining ESD protection.
Solution Approach 2:
The patent changes the doping concentration parameters of the semiconductor regions to achieve both low capacitance and high breakdown voltage. By carefully controlling the doping levels in the n-well, p-substrate, and their junction, the structure achieves ultra-low capacitance suitable for high-speed applications while maintaining the required ESD protection characteristics.
3Productivity
If the dopant concentrations are increased to reduce capacitance, then the capacitance decreases, but the breakdown voltage may be affected
Solution Approach 1:
The patent optimizes the doping concentration parameters to achieve the desired balance between capacitance and breakdown voltage. The n-well is doped at a first concentration, the p-substrate at a second concentration, and their junction is engineered to provide both low capacitance and high breakdown voltage characteristics. This parameter optimization resolves the trade-off between capacitance reduction and breakdown voltage maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a diode structure that consumes less silicon real estate and has significantly lower capacitance (1.3 pF) compared to conventional structures, enabling its use in high-speed signal applications while maintaining higher breakdown voltages.
Implementation Method 1
incorporating a p− epitaxial layer between two n+ epitaxial layers, reducing silicon usage and capacitance
Implementation Method 2
An electrostatic discharge (ESD) circuit is a circuit that protects an integrated circuit from voltage spikes
Implementation Method 3
when the voltage difference across the first and second nodes spikes up to be equal to or greater than the breakdown voltage, the ESD circuit provides a low-resistance current path
Data Source
AI summary
A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p− epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.