Bi-directional Self-aligned FET Capacitor Parasitic Reduction
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Solution Overview
Problem
Creating a field effect transistor (FET) capacitor that functions bidirectionally in silicon on insulator (SOI) technology is challenging due to parasitic resistances and capacitances, limiting its operation, especially when the gate voltage can be applied in either direction.
Innovation Solution
The method involves forming a gate stack with alternating dopant materials, where the source is P+ doped and the drain is N+ doped, and using angled implantation to create shadow regions, allowing for self-aligned diffusion contacts and reducing parasitic capacitance, enabling operation in both accumulation and inversion modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a body tie is used to enable accumulation mode operation in SOI, then the capacitor can store charge, but parasitic resistances and capacitances increase which limits operation
Solution Approach 1:
The patent extracts and removes the body tie connection that causes parasitic resistances and capacitances. By eliminating this harmful element while maintaining the capacitor's charge storage capability through alternative means, the invention resolves the contradiction between reliable operation and parasitic effects.
Solution Approach 2:
The patent introduces an intermediary structure (the self-aligned diffusion contact configuration with alternating dopant materials) that enables accumulation mode operation without requiring a direct body tie connection. This intermediary approach allows charge storage while avoiding the parasitic effects associated with traditional body ties.
2Adaptability or versatility
If source and drain are doped in the same manner for unidirectional operation, then the capacitor works in one direction, but it cannot operate in both bias directions
Solution Approach 1:
The patent applies local quality by creating alternating dopant material regions (N+ and P+) in specific locations within the channel. This localized differentiation of doping types enables the capacitor to respond to both positive and negative gate voltages, achieving bidirectional operation while maintaining a relatively simple overall structure.
Solution Approach 2:
The patent introduces asymmetry in the doping configuration with alternating N+ and P+ regions rather than uniform doping. This asymmetric structure creates different electrical characteristics in different regions, enabling the capacitor to function in both accumulation and inversion modes depending on the applied voltage polarity.
3Manufacturing precision
If conventional doping methods are used, then the process is straightforward, but shadow regions do not form and self-aligned diffusion contacts are not achieved
Solution Approach 1:
The patent transitions from conventional planar doping to angled ion implantation, adding a dimensional element to the doping process. By implanting dopant materials at specific angles rather than perpendicular to the surface, the gate structure casts shadow regions that automatically define the diffusion contact locations, achieving self-alignment without additional masking steps.
Solution Approach 2:
The gate structure serves a dual function: it acts as both the controlling electrode and as a shadow mask during angled ion implantation. This self-service approach allows the gate to automatically define the diffusion contact positions through the shadow regions it creates, eliminating the need for separate alignment procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-frequency switching and improved frequency response by reducing parasitic capacitance and enabling the FET capacitor to operate effectively in both bias directions, enhancing its performance in high-frequency settings.
Implementation Method 1
implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack
Data Source
AI summary
A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.