Bidirectional Hard IP Blocks Without RDL Signal Load
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Solution Overview
Problem
Conventional Serializer/Deserializer (SerDes) chiplets face inefficiencies in signal transmission due to high electrical loads from redistribution layers, leading to signal distortion and bandwidth limitations at high speeds, especially when using PAM4 modulation, as the increased load causes the signal 'eye' to shrink, making it difficult to differentiate between signal levels.
Innovation Solution
The implementation of hard IP blocks with keepout zones beneath interconnects eliminates the need for redistribution layers by positioning circuitry to serialize and deserialize signals beneath the surface, allowing surface interconnects to interface directly with external devices, thereby reducing resistive capacitive loads and maintaining signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redistribution layers are used to route signals from SerDes chiplets to external devices, then signal transmission is enabled, but electrical load increases causing signal distortion and bandwidth limitations
Solution Approach 1:
The patent extracts and eliminates the redistribution layer from the signal path by implementing through-silicon vias (TSVs) that create direct vertical connections between bond pads on the first die and bond pads on the second die. This removes the harmful redistribution layer entirely, allowing signals to bypass it and transmit directly between dies, thereby eliminating the electrical load problem while maintaining signal transmission capability
Solution Approach 2:
The patent transitions from planar signal routing (horizontal dimension) through redistribution layers to three-dimensional vertical routing using through-silicon vias. By moving signal transmission to the vertical dimension through TSVs, the design eliminates the need for horizontal redistribution layers and achieves direct die-to-die connectivity, reducing electrical load and improving signal quality
2Reliability
If through-silicon vias extend outside the perimeter of the SerDes chiplet, then direct connections are achieved, but large resistive capacitive load is created impacting signal quality
Solution Approach 1:
The patent applies local quality by confining through-silicon vias to extend only through the thickness of the die substrate without protruding beyond the die perimeter on either side. This localized approach ensures direct vertical connections are achieved while minimizing the area and thus the resistive capacitive load, improving signal quality compared to extended TSV designs
3Productivity
If multiple processing cores are used to increase computing efficiency, then processing speed improves, but data transmission bandwidth between processors and memories becomes a bottleneck
Solution Approach 1:
The patent merges the processor die and memory die into a single integrated package using direct die bonding with through-silicon via connections. This combining of previously separate components into a unified three-dimensional structure enables high-speed data transmission between processors and memories by eliminating external interconnects, thus resolving the bandwidth bottleneck while maintaining high computing efficiency
Data Source
AI summary
Hard IP blocks, such as SerDes chips, are designed with keepout zones beneath the surface interconnects, the keepout zones being spaces within the chip where there is no circuitry. Connections can be formed between surface interconnects on an under surface of the SerDes chip that faces the host die, and surface interconnects on an upper surface of the SerDes chip that interfaces without external devices. Accordingly, redistribution layers routing around an outer periphery of the SerDes chip are no longer needed, and the resistive capacitive load remains low so as not to adversely impact transmitted signals.