Bidirectional I/O Circuit With Floating N-Well Leakage Blocking
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Solution Overview
Problem
Existing bidirectional I/O circuits in integrated circuits face significant power consumption issues due to leakage currents when a chip in power-down mode is connected to a chip in normal mode, as high-level signals cause current to flow through parasitic diodes, leading to inefficiencies and design limitations.
Innovation Solution
A bidirectional I/O circuit with a floating N-well network and post driver control circuit that sets the input voltage level to VDD during power down mode, blocking leakage current paths through the output post driver using a PMOS transistor with a disconnected N-well and an ESD protection circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a chip is switched to power down mode to save power, then power consumption is reduced, but leakage current flows through parasitic diodes when connected to a normal mode chip
Solution Approach 1:
The patent extracts and removes the harmful leakage current path by physically disconnecting the N-well from the power supply in power-down mode. The N-well is separated from VDD through a switch circuit, eliminating the parasitic diode conduction path that causes leakage current to flow from the normal mode chip to the power-down mode chip.
Solution Approach 2:
The patent implements dynamic control of the N-well connection status based on operating mode. A mode detection circuit dynamically switches the N-well connection: connected to VDD in normal mode for proper transistor operation, and disconnected in power-down mode to prevent leakage. This dynamic reconfiguration allows the system to adapt its electrical characteristics to operational requirements.
2Loss of energy
If design is constrained to provide low-level signal to power-down mode I/O circuit, then leakage current is prevented, but design flexibility is limited
Solution Approach 1:
The patent introduces an intermediary N-well disconnection mechanism between the signal path and the power supply. This intermediary structure allows high-level signals to be received at the pad while preventing them from causing leakage current by blocking the current path at the N-well level, rather than constraining the signal level itself.
Solution Approach 2:
The patent changes the electrical parameter of the N-well potential rather than constraining the signal parameter. By dynamically adjusting the N-well voltage (connected to VDD or floating), the circuit maintains proper signal processing capability while preventing leakage current, allowing full signal level flexibility without compromising power efficiency.
3Reliability
If N-well is connected to VDD for normal operation, then PMOS transistors function correctly, but leakage current path is enabled when in power-down mode
Solution Approach 1:
The patent implements dynamic reconfiguration of the N-well connection based on operational mode detection. In normal mode, the N-well is connected to VDD to ensure proper PMOS transistor threshold voltage and operation. In power-down mode, the connection is dynamically disconnected to eliminate the leakage current path, achieving both reliable operation and power efficiency at different times.
Solution Approach 2:
The patent extracts the harmful leakage path by removing the N-well to VDD connection specifically during power-down mode. This selective extraction maintains the beneficial N-well connection during normal operation while eliminating the harmful effect during power-saving mode, resolving the contradiction between reliability and energy loss.
Data Source
AI summary
A bidirectional I/O circuit includes an output post driver configured to control an output signal of a bidirectional pad during a normal mode, a floating N-well network configured to apply a VDD-level bias to the output post driver based on an input signal of the bidirectional pad during a power down mode, and a post driver control circuit configured to set an input voltage level of the output post driver to a VDD level during the power down mode to prevent a leakage current path from being formed through the output post driver. A parasitic diode is formed between the drain of the first PMOS transistor and an N-well of the first PMOS transistor. The N-well of the first PMOS transistor is connected to the floating N-well network, and the source and the N-well of the first PMOS transistor are not physically connected to each other.