Bidirectional I/O Circuit Testing for Single-Scan Parametric Tests
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Solution Overview
Problem
Integrated circuit testing is time-consuming due to the need for separate scans for input and output parametric testing and quiescent current measurement, which can be inefficient and laborious.
Innovation Solution
A circuit I/O test system with bidirectional I/O circuits and testing logic that facilitates concurrent input and output parametric testing, along with quiescent current measurement, using a bidirectional switching control network and multiplexers to alternate between input and output modes during a single set of SoC scan data shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate scans are used for input and output parametric testing and quiescent current measurement, then testing completeness is ensured, but testing time increases
Solution Approach 1:
The patent merges input parametric testing, output parametric testing, and quiescent current measurement into a single scan sequence. The bidirectional I/O control circuit enables the I/O pad to function as both input and output during different phases of the same scan, allowing all tests to be performed concurrently without requiring separate scan operations.
Solution Approach 2:
The I/O pad is designed with multi-functionality through the bidirectional I/O control circuit. It can serve as input for parametric testing, output for parametric testing, and power supply for quiescent current measurement within the same scan cycle, making a single scan structure capable of performing multiple distinct testing functions.
2Productivity
If bidirectional I/O control is implemented for concurrent testing, then testing efficiency improves, but device complexity increases
Solution Approach 1:
The bidirectional I/O control circuit dynamically switches the I/O pad between input and output modes based on the testing phase. The control logic uses scan enable signals and clock signals to transition the I/O pad between different functional states, enabling flexible reconfiguration during the scan sequence without requiring separate hardware paths.
Data Source
AI summary
One example includes a circuit. The circuit includes a circuit core configured to perform an operational function and scan-chain registers configured to propagate a set of system-on-chip (SoC) scan data that is input to the circuit generated from an automatic test pattern generator (ATPG) to set a different device state of the circuit core at each shift of the SoC scan data. The circuit further includes a plurality of bidirectional input/output (I/O) circuits each comprising a bidirectional I/O control and testing logic, the testing logic being configured to alternately facilitate input parametric testing and output parametric testing of an I/O pad of the respective bidirectional I/O control at each shift of the set of SoC scan data via a pin parametric measurement unit (PPMU).