Bidirectional JFET Driver Circuitry for High-Voltage SiC Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing bidirectional semiconductor power transistor devices face challenges with P-type wafer availability, high-voltage operation, and conductivity issues, particularly in Silicon Carbide devices, due to limitations in P-type dopant control and avalanche breakdown, leading to inefficiencies in AC switching and high-voltage handling.
Innovation Solution
A method of driving bidirectional semiconductor power transistors using a high-side P+ and N+ electrode configuration, allowing current steering and exploiting turn-on and turn-off loss properties without external power, and employing a controller to determine the lowest potential side for driving, along with a PWM signal to manage switches, enabling efficient AC switching and high-voltage handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If P-type wafer is used for bidirectional device construction, then hole conduction provides adequate conductivity, but lack of suitable high-voltage P-type wafer limits operation to below 3 kV
Solution Approach 1:
The patent inverts the conventional approach by using an N-type wafer instead of a P-type wafer as the base substrate. This allows the device to achieve high-voltage operation capability (>3 kV) while maintaining manufacturing feasibility, as N-type high-voltage wafers are readily available through NTD processing. The device structure is designed to operate with electron conduction as the primary mechanism, reversing the traditional hole conduction approach.
Solution Approach 2:
The patent changes the fundamental doping type parameter from P-type to N-type for the wafer substrate. This parameter change enables access to suitable high-voltage N-type wafers with uniform phosphorus concentration achieved through NTD, thereby supporting operation above 3 kV while maintaining manufacturing ease.
2Ease of manufacture
If PNP configuration is used with N-type wafer, then device structure is simplified, but hole conduction reduces conductivity by 2× compared to electron conduction
Solution Approach 1:
The patent inverts the conventional PNP configuration by implementing an NPN configuration where electron conduction dominates. This inversion restores the superior conductivity characteristics (2× higher than hole conduction) while maintaining the simplified device structure achieved by using a single N-type wafer substrate. The electron-based conduction path provides both structural simplicity and high conductivity.
3Reliability
If separate driver circuits are used for front and rear control electrodes, then high-voltage potential difference (1000V) between sides is managed, but device complexity and cost increase
Solution Approach 1:
The patent merges the driver circuit requirements by enabling the device to be controlled from a single side only. This is achieved through the asymmetric device structure where the N-type wafer base with appropriately designed control electrodes allows full device operation from one control interface, eliminating the need for separate driver circuits on both sides while still managing the 1000V potential difference reliably.
Solution Approach 2:
The patent makes the device universally controllable from either the front or rear side, providing multi-functionality in the control interface. The device structure is designed so that a single driver circuit can effectively control device operation regardless of which side is used as the control interface, reducing overall system complexity while maintaining high-voltage management capability.
Data Source
AI summary
Double sided versions of several power transistor types are devices that are already known in the literature. Devices built in this configuration are generally required to have a separate driver circuit to control the front and rear control electrodes and provide the gate or base voltage and/or currents for the power switch. This is because there may be of the order of 1000V potential-difference between the frontside and rearside potentials when the transistor is in the off condition—and a single integrated circuit cannot generally sustain this within a single package. The NPN configuration is preferred in this case to benefit from electron conduction for the main power path between the emitters. However, problems arising when using a P-type wafer. The present invention seeks to avoid the use of P-type wafers while still getting the higher conduction performance of NPN operation.