Bidirectional Level Translator Buffer for Low-Noise High Data Rates
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Solution Overview
Problem
Existing bidirectional voltage level translators face challenges in reducing noise during voltage translations, particularly when converting low-to-high voltages, which affects the monotonic behavior of output signals and reduces data rates.
Innovation Solution
The proposed solution involves a bidirectional voltage level translator chip with an output buffer that combines output edge control (staggering) for low-to-high voltage translation and output boosting for high-to-low voltage translation, utilizing a combination of low voltage threshold and standard P-type and N-type field effect transistors, along with booster transistors to minimize noise and maintain monotonic behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If output edge control (staggering) is used for low-to-high voltage translation, then noise is reduced, but data rate decreases below acceptable levels
Solution Approach 1:
The output buffer is segmented into multiple parallel transistor paths: standard Vt transistors for normal operation and low Vt transistors for noise reduction during specific transitions. This segmentation allows the circuit to achieve both low noise (through selective use of low Vt transistors during low-to-high transitions) and high data rate (through parallel paths and selective activation)
Solution Approach 2:
The circuit dynamically switches between different transistor configurations based on the translation direction. During low-to-high voltage translation, low Vt transistors are activated to reduce noise. During high-to-low translation, standard Vt transistors operate at full speed. This dynamic adaptation resolves the contradiction by optimizing performance for each translation direction independently
2Stability of the object's composition
If noise reduction techniques are applied, then monotonic behavior is improved, but data rate is reduced
Solution Approach 1:
Different transistor threshold voltages are applied locally to different parts of the circuit based on the translation direction. Low Vt transistors are used specifically for low-to-high translation to ensure monotonic behavior and reduce noise, while standard Vt transistors handle high-to-low translation at high speed. This local differentiation resolves the contradiction by applying noise reduction only where needed
3Adaptability or versatility
If voltage range is extended to support lower voltages, then adaptability is improved, but noise coupling between channels increases
Solution Approach 1:
The low Vt transistors act as intermediaries during low-to-high voltage translation, providing a controlled path that reduces noise coupling to other channels. The separate control signals for low Vt and standard Vt transistors allow precise timing control, ensuring that noise-generating transitions are minimized while supporting the extended voltage range from 0.65V to 3.6V
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces noise and maintains monotonic behavior across a wide voltage range, allowing for increased data rates and improved signal integrity by reducing the impact of parasitic noise from low-to-high voltage conversions on high-to-low voltage translations.
Implementation Method 1
a low voltage threshold (Vt) P-type field effect transistor (PFET) coupled between the second supply voltage and the output signal, a gate of the low Vt PFET being coupled to be controlled by a first gate control signal; a low Vt N-type field effect transistor (NFET) coupled between the output signal and the ground rail
Implementation Method 2
a first plurality of PFETs coupled in parallel between the second supply voltage and the output signal, the first plurality of PFETs having a standard Vt; a first plurality of NFETs coupled in parallel between the output signal and the ground rail, the first plurality of NFETs having a standard Vt
Implementation Method 3
a third resistor coupled in series with a first booster NFET between the second supply voltage and the output signal, the first booster NFET receiving a first booster control signal on a gate; and a second booster NFET being coupled between the output signal and the ground rail, the second booster NFET receiving a second booster control signal on a gate
Data Source
AI summary
A level translator translates signals between first and second voltage domains. An output buffer thereof includes a plurality of PFETs coupled in parallel between a second domain's output supply voltage and an output signal and a plurality of NFETs coupled in parallel between the output signal and the ground rail. Each gate of the plurality of PFETs is coupled to a respective first resistor; the first resistors are coupled in series and receive a first gate control signal. Each gate of the plurality of NFETs is coupled to a respective second resistor; the second resistors are coupled in series and receive a second gate control signal. A first booster NFET is coupled between the output supply voltage and the output signal and a second booster NFET is coupled between the output signal and the ground rail. The booster NFETs receive control signals that operate in the first voltage domain.