Bidirectional Memory Clock Conversion for Display Data Transfer
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Solution Overview
Problem
Existing liquid crystal display apparatuses face challenges in reducing data transfer speed without increasing radiation noise, substrate area, and power consumption, while maintaining timing constraints, due to the need for faster output data transfer and the limitations of existing methods like dividing data into odd and even numbers or using line memories.
Innovation Solution
A display apparatus with N bidirectional memories that allow simultaneous data writing and reading, a phase locked loop for clock conversion, and controllers for synchronized data transfer to N driver ICs, where the output clock frequency is lower than the input clock frequency but higher than 1/N times, enabling reduced output data transfer speed and securing a blank period without relying on input video signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer speed is increased to transmit more bits per wire, then the amount of data transfer per signal wire is improved, but radiation noise increases due to stray capacitance and wiring inductance
Solution Approach 1:
The patent divides the high-speed data transfer into multiple lower-speed parallel channels using multiple driver ICs. Each driver IC receives data at a lower clock frequency (output clock from PLL), splitting the total data stream across N drivers. This segmentation reduces the transfer speed per wire while maintaining overall throughput, thereby reducing radiation noise from stray capacitance and inductance.
2Object-generated harmful factors
If data transfer speed is reduced by dividing data into odd and even numbers, then radiation noise is suppressed, but the number of data wires and substrate area double
Solution Approach 1:
The patent employs bidirectional memories that can simultaneously perform both data writing and data reading operations. This multi-functionality allows the same memory resource to serve dual purposes: accepting input data while concurrently supplying output data to driver ICs. By eliminating the need for separate odd/even data paths, the substrate area is reduced while maintaining noise suppression benefits.
Solution Approach 2:
The bidirectional memories enable continuous data flow by writing and reading simultaneously without interruption. This continuous operation eliminates the need to halt data transfer for memory switching or buffering, maintaining high productivity while using fewer wires compared to the odd/even division method.
3Speed
If line memories are used to reduce transfer speed, then output data speed is reduced, but at least two horizontal periods of memory are needed to avoid data overwriting
Solution Approach 1:
The patent uses bidirectional memories with dynamic control of data flow directions. The memories can switch between writing-mode and reading-mode operations under controller management, allowing flexible data handling. This dynamic operation enables the use of smaller memory capacity (less than two horizontal periods) by intelligently managing data write/read timing and avoiding overwriting through coordinated control signals.
4Speed
If output data is divided into two for transfer, then transfer speed is reduced by half, but the number of data clocks during blank period is also reduced by half, possibly resulting in insufficient timing constraints
Solution Approach 1:
The patent employs a Phase Locked Loop (PLL) to generate an output clock with a frequency that is lower than the input clock but higher than 1/N times the input clock. This parameter adjustment of the clock frequency allows flexible control of the data transfer rate. By optimizing the output clock frequency, the system achieves reduced transfer speed while maintaining sufficient blank period timing margins for driver IC operations, avoiding the timing constraint issues of simple frequency division.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution suppresses output data transfer speed by approximately 40-60% of the input data rate, secures a timing margin (blank period), and reduces the need for additional components and noise countermeasures, allowing for flexible driver IC compatibility and reduced substrate area, thus addressing the constraints of existing technologies.
Implementation Method 1
a phase locked loop that converts an input clock to an output clock
Data Source
AI summary
A display apparatus according to the present invention includes: N driver ICs (first to third driver ICs); N or more bidirectional memories (first to third bidirectional memories) that simultaneously allow data writing and data reading; a phase locked loop that converts an input clock to an output clock; a write controller that writes data to the plurality of bidirectional memories in synchronization with the input clock; and a read controller that reads the data from the plurality of bidirectional memories and causes the data to be output to the plurality of driver ICs in synchronization with the output clock. A frequency of the output clock is smaller than a frequency of the input clock and is larger than 1/N times the frequency of the input clock.