Bidirectional Processing Element Array for Neural Network Accelerator

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Solution Overview

Problem

The increasing demand for hardware resources and memory access frequency in implementing convolutional neural networks (CNNs) poses a challenge for efficient processing in hardware form, necessitating a technology to reduce these limitations.

Innovation Solution

A neural network accelerator featuring a bidirectional processing element array that performs calculations using kernel and feature map data, minimizing additional processing blocks and optimizing data exchange between memory and processing elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If CNN is implemented in hardware form using semiconductor device, then calculation performance is improved, but hardware resources and memory access frequency increase

Engineering Contradiction:
Improvecalculation performanceVSAvoidhardware resources
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The processing element array is divided into multiple processing elements (PEs) arranged in a two-dimensional grid, where each PE handles a specific portion of the convolution calculation. This segmentation allows parallel processing of different regions of the feature map, improving calculation performance while distributing hardware resources efficiently across the array.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension to the data flow by implementing sequential data movement through the PE array. Data is fed into the array over multiple time steps, with each PE processing data as it flows through the array. This temporal dimension allows the same hardware resources to be reused across multiple calculations, reducing the overall hardware resource requirement while maintaining high calculation performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If CNN is implemented in hardware form using semiconductor device, then calculation performance is improved, but memory access frequency increases

Engineering Contradiction:
Improvecalculation performanceVSAvoidmemory access frequency
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

Input data and filter data are loaded into the processing element array in advance before the actual convolution calculation begins. This preliminary loading allows the data to be readily available in the array's internal storage, eliminating the need for frequent memory accesses during the calculation phase and reducing overall memory access frequency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements continuous data flow through the PE array, where data is processed sequentially as it moves through the array without interruption. This continuous processing minimizes idle time and reduces the need for repeated memory accesses, as the system maintains a steady stream of data through the processing elements throughout the calculation.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If bidirectional processing element array is used, then data exchange efficiency is improved, but processing element arrangement complexity increases

Engineering Contradiction:
Improvedata exchange efficiencyVSAvoidprocessing element arrangement
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements asymmetric data flow directions within the PE array. Data enters the array in one direction (e.g., from left to right for input features, from top to bottom for filter values) and exits in a different direction (e.g., results are collected from right to left, bottom to top). This asymmetric arrangement optimizes data exchange efficiency by aligning data flow with the natural progression of convolution operations, while the underlying grid structure maintains relative simplicity.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS11507429B2Neural network accelerator including bidirectional processing element array
Publication Date: 2022.11.22 ELECTRONICS & TELECOMM RES INST
  • US11507429B2 patent drawing
  • US11507429B2 patent drawing
  • US11507429B2 patent drawing

AI summary

Provided is a neural network accelerator which performs a calculation of a neural network provided with layers, the neural network accelerator including a kernel memory configured to store kernel data related to a filter, a feature map memory configured to store feature map data which are outputs of the layers, and a Processing Element (PE) array including PEs arranged along first and second directions, wherein each of the PEs performs a calculation using the feature map data transmitted in the first direction from the feature map memory and the kernel data transmitted in the second direction from the kernel memory, and transmits a calculation result to the feature map memory in a third direction opposite to the first direction.