Bi-directional RC-clamp ESD Protection for Mixed-Voltage ICs
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Solution Overview
Problem
Existing ESD protection methods for semiconductor integrated circuits are inadequate as they rely on relative supply rail voltages and sequencing, limiting their effectiveness in providing bi-directional ESD conduction paths and increasing the chip area required for protection, especially in mixed-voltage ICs with isolated power and ground rails.
Innovation Solution
A bi-directional RC-clamp system is introduced, comprising head-to-head diodes, series and anti-parallel RC networks, and complementary transistors, which allows ESD conduction between any pair of supply rails independently of voltage levels and sequencing, ensuring minimal area consumption and robust protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional RC-controlled ESD clamp is used to provide ESD conduction path between supply rails, then ESD protection is achieved, but the circuit cannot provide protection when the supply rail voltages are reversed or during non-sequenced power-up, and larger chip area is required
Solution Approach 1:
The patent employs asymmetric transistor pairs (PMOS and NMOS) configured in a push-pull arrangement where each transistor type is optimized for its specific conduction direction. The PMOS transistor conducts when Rail1 is higher than Rail2, while the NMOS transistor conducts when Rail2 is higher than Rail1, creating asymmetric protection paths tailored to each voltage condition without requiring separate circuits for each scenario.
Solution Approach 2:
The dual-transistor clamp circuit serves multiple functions within a single integrated structure: it provides ESD protection for both voltage polarities (Rail1>VSS and Rail2>VSS), operates during non-sequenced power-up, and maintains high impedance during normal operation. This universal protection mechanism eliminates the need for separate protection circuits for different voltage conditions.
2Reliability
If separate ESD protection circuits are used for different voltage conditions and power sequences, then comprehensive ESD coverage is achieved, but chip area increases significantly
Solution Approach 1:
The patent merges multiple ESD protection functions into a single integrated clamp circuit. The PMOS and NMOS transistors are combined in a push-pull configuration that simultaneously handles both voltage polarities and power sequence conditions. This consolidation achieves comprehensive ESD coverage while occupying minimal chip area compared to using separate protection circuits for each condition.
Solution Approach 2:
The single clamp circuit performs multiple protection functions: it protects against ESD on Rail1 when Rail1>VSS, protects against ESD on Rail2 when Rail2>VSS, and operates during non-sequenced power-up. This multi-functional design eliminates the need for multiple separate circuits, significantly reducing the required chip area.
3Use of energy by moving object
If the ESD clamp remains in high impedance state during normal operation, then power consumption is minimized, but the clamp must quickly transition to low impedance during ESD events
Solution Approach 1:
The clamp circuit dynamically transitions between high impedance and low impedance states based on the ESD detection condition. During normal operation, both transistors remain off maintaining high impedance and minimal power consumption. When an ESD event is detected (voltage difference exceeds threshold), the appropriate transistor quickly switches to low impedance state to conduct the ESD current, achieving fast response without continuous power consumption.
Solution Approach 2:
The circuit incorporates implicit feedback through the voltage difference detection mechanism. The gate-source voltage of each transistor is directly controlled by the voltage difference between the rails, creating a natural feedback loop that automatically switches the transistor state based on the ESD condition, ensuring fast response while maintaining low power consumption during normal operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bi-directional RC-clamp system provides efficient ESD protection across various voltage levels without the need for sequential power-up, reduces chip area, and maintains high impedance during normal operation, effectively addressing the limitations of prior art by ensuring reliable ESD discharge without degrading performance.
Implementation Method 1
The RC time constant of the RC-circuit R11-C11 is kept higher than the rise time of ESD voltage pulse at Rail11. Thus the voltage level of VG is increased much slower than the voltage level on Rail11.
Implementation Method 2
The turned-on N12 provides a low impedance path between rails Rail11 and Rail12 that discharges the ESD current and clamps the ESD voltage across them.
Data Source
AI summary
The embodiments of the present invention introduced and taught herein are directed to a whole-chip ESD protection arrangement that is independent of relative supply rail voltage and supply sequencing, thereby enabling ESD conduction path during ESD event and isolating the ESD conduction path during the power up and power down modes of the chip. An embodiment of the present invention uses the bi-directional R-C clamp with transistorized arrangements between powered rails and avoids the drawback of using uni-directional Clamps or diode array for clamping that consumes large silicon area, requires power sequencing and is prone to noise coupling between power rails.