Bidirectional RC Glitch Detectors for Low-Power EMP Detection

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Solution Overview

Problem

Existing integrated circuit security measures are inadequate in detecting electromagnetic pulse (EMP) glitches and power supply glitches, particularly in IoT applications, as current detection methods are either power-intensive or insufficiently sensitive, allowing unauthorized access and tampering.

Innovation Solution

Implementing RC-based glitch detectors with capacitors and resistors coupled to supply voltage nodes, combined with amplifiers and latches, to accurately detect positive and negative voltage glitches, ensuring minimal power consumption and high sensitivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If synchronous detection techniques using high frequency clock signal (>1 GHz) are used to detect EMP attacks, then detection capability is improved, but power consumption increases significantly

Engineering Contradiction:

Improvedetection capabilityVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent changes the detection parameter from high frequency clock signal (>1 GHz) to RC time constant parameters (R1C1 and R2C2). By adjusting resistance and capacitance values, the circuit achieves sensitivity to short EMP pulses without requiring high frequency operation, thus reducing power consumption while maintaining detection capability.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical/electronic clock signal-based detection system with an RC circuit-based detection system. The RC time constants create voltage pulses in response to EMP attacks, which are then detected by comparators, substituting the need for high frequency clock signals and reducing power requirements.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If RC-based glitch detectors with amplifiers and latches are implemented, then detection sensitivity is improved, but device complexity increases

Engineering Contradiction:

Improvedetection sensitivityVSAvoidcircuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the detection function into separate segments: RC filtering stage (R1C1, R2C2), amplification stage (op-amps), and latching stage (D flip-flops). Each segment performs a specific function, allowing independent optimization and simplifying the overall design while achieving high sensitivity through the combined effect of these segmented components.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Effectively detects and responds to both positive and negative glitches, reducing the risk of unauthorized access by triggering appropriate security measures, while maintaining low power consumption.

Implementation Method 1

A capacitor is coupled between the supply voltage node and a first node and a resistor is coupled between the first node and a ground node. In response to a positive glitch occurring on the supply voltage node, a positive voltage pulse corresponding to the voltage glitch is generated on the first node

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

Methodology Applied

Scientific EffectRC circuit transient response:

Implementation Method 3

The latch circuit is clocked by the output signal supplied by the first circuit, and a state of the latch circuit changes to supply an asserted latch output signal indicative of the positive glitch

Methodology Applied

Scientific EffectElectronic signal detection and latching:

Data Source

PatentUS12392822B2Voltage glitch detectors

Publication Date: 2025.08.19 SILICON LABORATORIES INC

AI summary

Positive and negative glitch detectors detect glitches on a supply voltage node. The positive glitch detector has a capacitor and a resistor serially coupled between the supply voltage node and ground. An amplifier is coupled to a first node between the capacitor and resistor. A positive glitch results in the glitch on the first node (normally biased low) and generation of a clock pulse by the amplifier that causes a latch to assert its output to indicate the positive glitch. The negative glitch detector has a capacitor and resistor coupled in parallel between the supply voltage node and a second node. A negative glitch on the supply voltage node decreases the voltage on the second node (normally biased high) and an inverting amplifier coupled to the second node generates a clock pulse to cause a latch to assert its output to indicate the negative voltage glitch.