Bi-Directional Scan Flip-Flop Circuit for Reversible DFT Scanning
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Solution Overview
Problem
Current design-for-test (DFT) methods for integrated circuits (ICs) face limitations in error detection due to fixed scan directions, which hinder efficient identification of failure sites and compromise test efficiency in large IC designs.
Innovation Solution
A scan flip-flop circuit with selectable scan directions, incorporating selection circuits and tri-state drivers, allows for improved error detection by enabling data bit propagation in both forward and reverse directions, enhancing test efficiency and failure site identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed scan direction is used in DFT methods, then the circuit structure is simple, but error detection capability is limited
Solution Approach 1:
The patent implements dynamic scan direction control by introducing a direction control signal that can switch between forward and reverse scan modes. The scan chain structure is made adaptable through dynamic selection of scan direction, allowing the same hardware to perform different test patterns. This resolves the contradiction by enabling enhanced error detection capability through dynamic configuration without permanently increasing circuit complexity.
Solution Approach 2:
The patent changes the operational parameter of scan direction from fixed to variable. By introducing a direction control signal that can take different values (forward/reverse), the system can switch between different test modes. This parameter change enables comprehensive error detection while maintaining the same physical circuit structure, thus resolving the contradiction between detection capability and circuit complexity.
2Productivity
If a fixed scan direction is used, then the circuit is easier to operate, but test efficiency is compromised
Solution Approach 1:
The system employs dynamic scan direction switching controlled by a direction control signal. This allows the test system to adaptively change scan direction based on test requirements, improving test efficiency for large IC designs. The dynamic control mechanism balances operational complexity with productivity by providing automated direction selection rather than manual reconfiguration.
Solution Approach 2:
The scan chain is designed to perform multiple functions by supporting both forward and reverse scan directions. This multi-functionality allows the same circuit structure to handle different test scenarios efficiently, improving overall test productivity. The universal design enables a single circuit to replace what would otherwise require multiple specialized circuits for different scan directions.
3Measurement precision
If fixed scan direction is implemented, then device complexity is low, but failure site identification is hindered
Solution Approach 1:
The patent implements dynamic scan direction control that can switch between forward and reverse modes based on test requirements. This dynamic capability enables precise failure site identification by allowing testers to approach suspected defect locations from different directions. The increased measurement precision in failure localization is achieved through dynamic configuration rather than permanent structural complexity.
Solution Approach 2:
The scan chain is segmented into individual scan flip-flops that can be independently controlled. This segmentation allows the test system to isolate and identify specific failure sites by controlling which segments are scanned in which direction. The segmented structure enables precise failure localization without requiring the entire circuit to be complex, as only the necessary segments are configured for each test.
Data Source
AI summary
A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.