Bi-Directional Serializer Link on One Line With Low Signal Distortion

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor devices face challenges in increasing bandwidth without adding input and output pins or increasing data rates, which leads to signal distortion due to inter-symbol interference.

Innovation Solution

Implementing a semiconductor device with a serializer, transmission circuit, and reception circuit that utilize delay circuits to synchronize and superpose signals, and employ reference voltage levels for accurate signal detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of input and output pins is increased to increase bandwidth, then the bandwidth is improved, but the physical space of the semiconductor package is exceeded

Engineering Contradiction:
ImprovebandwidthVSAvoidphysical space of semiconductor package
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent merges bidirectional communication channels into a single signal transmission line. Multiple data signals (first transmission signal from first semiconductor device and second transmission signal from second semiconductor device) are superposed on the same physical transmission line, allowing simultaneous two-way communication without requiring separate pins for each direction, thus increasing bandwidth while conserving package space.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If the data rate is increased to increase bandwidth, then the bandwidth is improved, but inter-symbol interference is increased due to channel loss

Engineering Contradiction:
ImprovebandwidthVSAvoidsignal quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary equalization at the transmitter side to pre-compensate for channel loss effects. The transmission signals are pre-distorted in a controlled manner so that after passing through the lossy channel, the received signals maintain proper amplitude relationships. This preliminary action prevents inter-symbol interference before it occurs, allowing high data rates without sacrificing signal quality.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If simultaneous bi-directional communication is implemented by superposing transmission signals, then bandwidth is increased without increasing pins or data rate, but signal distortion occurs

Engineering Contradiction:
ImprovebandwidthVSAvoidsignal integrity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent employs parameter changes including differential voltage levels and controlled impedance matching to manage signal superposition. By carefully selecting voltage levels for transmitted signals and adjusting impedance parameters of the transmission line and terminal circuits, the system enables clean signal separation at the receiver despite simultaneous bidirectional transmission, maintaining signal integrity while achieving high bandwidth.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250365123A1Semiconductor device and semiconductor system performing simultaneous bi-directional communication
Publication Date: 2025.11.27 SK HYNIX INC
  • US20250365123A1 patent drawing
  • US20250365123A1 patent drawing
  • US20250365123A1 patent drawing

AI summary

A semiconductor device includes a serializer, a transmission circuit, and a reception circuit. The serializer is configured to generate transmission data from first and second output data signals based on first and second transmission clock signals. The transmission circuit is configured to drive, based on the transmission data, a node that is electrically coupled to a signal transmission line. The reception circuit is configured to generate reception data, based on the first and second reception clock signals, the first and second output data signals, and a voltage level of the node.