Bidirectional Shift Register with Three-Phase Clock Control
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Solution Overview
Problem
Conventional bidirectional shift registers for liquid crystal display devices face challenges in achieving a compact circuit size while maintaining stable operation, often resulting in large frame-edges and potential electrical variations that can impair circuit stability.
Innovation Solution
A bidirectional shift register design utilizing a selection circuit that controls unit registers with three or more clock signals of different phases, allowing for selective clock signal input based on a setting signal to reset and operate the circuit efficiently, thereby reducing circuit size and preventing electrical potential variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional bidirectional shift register designs are used, then bidirectional scanning functionality is achieved, but circuit size becomes large resulting in enlarged frame-edges
Solution Approach 1:
The patent merges the reset circuit functionality into the existing clock signal distribution infrastructure by using the same three-phase clock signals (CLK1, CLK2, CLK3) that control the unit registers also control the reset circuits. This eliminates the need for separate reset signal lines and reduces circuit area while maintaining bidirectional scanning capability
Solution Approach 2:
The clock signal distribution network serves dual purposes: it simultaneously controls the operation of unit registers and the reset circuits. The three-phase clock signals are universally applied to both forward-direction and reverse-direction reset circuits, making the clock system multi-functional and reducing overall circuit complexity
2Adaptability or versatility
If conventional bidirectional shift register designs are used, then bidirectional scanning is enabled, but electrical potential variations occur that can impair circuit stability
Solution Approach 1:
The patent implements feedback mechanisms where the clock signals are distributed in a controlled sequence through the three-phase system. The phased clock distribution provides timing feedback control that ensures reset operations are synchronized with register operations, preventing electrical potential variations and maintaining circuit stability during bidirectional scanning
Solution Approach 2:
The reset circuits are activated periodically through the three-phase clock signals in a controlled sequence. This periodic activation ensures that reset operations occur at appropriate timing intervals, preventing electrical potential variations by synchronizing reset actions with the scanning rhythm rather than allowing random or unsynchronized reset events
3Area of stationary object
If circuit size is reduced, then frame-edge becomes narrower, but circuit stability may be compromised
Solution Approach 1:
By merging the reset circuit control into the existing clock signal distribution system, the patent reduces circuit area while maintaining stability through the proven clock synchronization mechanism. The shared clock infrastructure ensures that even in a compact design, timing relationships are preserved and circuit stability is maintained
Data Source
AI summary
A device, in which circuit size is small and operation is stable, comprises a plurality of serially connected unit registers (shift registers) in which transfer is controlled by any of three or more clock signals each having a different phase, and a setting signal which determines shift direction; and a selection circuit (switch array) which can select at least one clock signal from the three or more clock signals in accordance with the setting signal; wherein the unit registers are put in a reset state by one clock signal selected by the selection circuit, corresponding to each of the unit registers