Bidirectional Shift Register Circuit With Unified Clock-Phase Control
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Solution Overview
Problem
Existing bidirectional shift registers face challenges in miniaturization and stability due to the need to switch circuit structures based on direction, leading to unstable operation and through currents, which are unsuitable for high-resolution image display devices.
Innovation Solution
A bidirectional shift register design with cascaded unit register circuits, including main and dummy stages, and a clock signal generating portion that supplies n-phase clock pulses for forward and reverse directions, along with a trigger signal generating portion to stabilize operation, allowing for stable bidirectional shift operation with a simple circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bidirectional shift register switches circuit structures based on direction, then bidirectional operation is enabled, but circuit complexity increases and stability deteriorates
Solution Approach 1:
The patent applies universality by designing a unified circuit structure that performs both forward and reverse shift operations without requiring separate circuit paths. The same unit register circuit responds to different clock signal phases (CK0-CK3) to achieve bidirectional operation, eliminating the need for structure switching and reducing overall circuit complexity.
Solution Approach 2:
The patent implements dynamics by using dynamic clock signal phase selection to control shift direction. The clock signal generating portion dynamically selects which phase of the clock signals is applied to which unit register circuit based on the desired shift direction, allowing the circuit to adapt its behavior without changing its physical structure.
2Adaptability or versatility
If bidirectional shift register switches circuit structures based on direction, then bidirectional operation is enabled, but operation stability deteriorates due to through currents
Solution Approach 1:
The patent applies preliminary action by pre-configuring the clock signal phases and their timing relationships before shift operations begin. The clock signal generating portion establishes proper phase relationships in advance, ensuring that clock signals are applied in the correct sequence for the desired shift direction, which prevents unstable operation and through currents during actual data transfer.
Solution Approach 2:
The patent implements feedback through the cascaded connection of unit register circuits where each stage's output feeds into the next stage's input. This creates a controlled signal flow that prevents unstable operation and through currents by ensuring signals propagate in the intended direction only.
3Manufacturing precision
If unit register circuits are reduced in size for high resolution, then arrangement density improves, but circuit miniaturization becomes more difficult
Solution Approach 1:
The patent applies merging by combining multiple functions into a single unit register circuit structure. The circuit integrates set/reset functionality, bidirectional shift capability, and clock signal response all in one compact unit, eliminating the need for separate circuits for each function and enabling further miniaturization while maintaining high arrangement density.
Solution Approach 2:
The patent implements segmentation by dividing the shift register into multiple identical unit register circuits that can be cascaded. Each unit is a self-contained module with standardized interfaces, allowing for systematic scaling and optimization. This modular approach enables precise control over circuit size and facilitates miniaturization through repeated use of optimized unit cells.
Data Source
AI summary
A shift register circuit, including: a plurality of clock signal lines each supplying a plurality of clock pulses respectively; phases of the plurality of clock pulses are different from each other, and a plurality of cascade-connected register circuits including a top register circuit, a bottom register circuit, and main register circuits are provided between the top register circuit and the bottom register circuit. Each of the plurality of cascade-connected register circuits includes a set terminal, a reset terminal, a first node, a second node, a second node reset terminal, an output part, a second output part, a first node set part, a second node set part, a first node control part, and a second node control part.