Bi-directional Shift Register Circuit for Display Panels
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Solution Overview
Problem
Conventional shift registers in display devices are limited to single-direction signal output, which fails to meet the requirements of rotating displays and increases power consumption due to larger transistors needed for shorter falling times of output pulses.
Innovation Solution
A bi-directional shift register circuit with multiple shift registers, each receiving four clock signals with rising and falling edges closely aligned, allowing for reduced falling times and power consumption by discharging output voltage through multiple transistors simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional single-direction shift registers are used, then the circuit structure is simple, but the falling time of output pulses is long and power consumption is high
Solution Approach 1:
The shift register is designed to dynamically switch between forward and reverse scan directions based on control signals. The circuit structure allows flexible operation modes where the scanning direction can be changed by controlling the timing relationships between clock signals, enabling the same hardware to adapt to different display requirements without increasing power consumption
Solution Approach 2:
The output discharge path is segmented into multiple independent transistor channels (first discharge transistor and second discharge transistor) that can operate separately or simultaneously. This segmentation allows the circuit to discharge output voltage through multiple parallel paths, reducing the falling time without requiring a single oversized transistor that would increase power consumption
2Speed
If transistor size is increased to reduce falling time, then the falling time of output pulses is reduced, but the power consumption and circuit area increase
Solution Approach 1:
The discharge function is divided into multiple transistor components working in parallel. Instead of using one large transistor, the circuit uses multiple smaller transistors (first discharge transistor and second discharge transistor) that can simultaneously discharge the output voltage, achieving fast falling time while keeping individual transistor sizes small and power consumption low
Solution Approach 2:
The circuit uses periodic clock signals with specific timing relationships to control the discharge transistors. By synchronizing the clock phases, the transistors are activated in a coordinated periodic manner that maximizes discharge efficiency during critical periods while minimizing power consumption during non-critical periods
3Adaptability or versatility
If single scanning direction is used, then the circuit operation is simple, but the adaptability to rotating displays is poor
Solution Approach 1:
The shift register implements dynamic direction control by changing the phase relationships between multiple clock signals. The same physical circuit can switch between forward scan and reverse scan modes by adjusting which clock signal leads or lags, providing adaptability to rotating displays without requiring separate hardware for each direction
Solution Approach 2:
The shift register circuit is designed with universal functionality to support both forward and reverse scanning operations using the same hardware components. Multiple clock input terminals and configurable timing relationships allow the circuit to perform multiple scanning directions and adapt to different display orientations, making a single circuit serve multiple purposes
Data Source
AI summary
A display panel includes shift registers coupled in serial. At least one of the shift registers includes an input circuit, an output circuit and a control circuit. The input circuit is coupled to a first input terminal and a second input terminal for respectively receiving a first input signal and a second input signal. The output circuit is coupled to a first clock input terminal for receiving a first clock signal and outputting a pulse signal at an output terminal according to the first clock signal. The control circuit is coupled to the output circuit via a first control node, a second control node and a third control node and controls voltages at the first control node, the second control node and the third control node according to the first input signal or the second input signal, and further controls operations of the output circuit.