Bidirectional Shift Register Using Four-Phase Clocks for Stable Direction Switching
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Solution Overview
Problem
Bidirectional shift registers face challenges in miniaturization and stability due to complex circuit structures and timing inaccuracies, particularly when switching directions, which can lead to unstable transistor operation and through currents.
Innovation Solution
A bidirectional shift register design with a simple circuit structure that uses cascaded unit register circuits driven by four-phase clock signals, where the clock signal generating portion generates overlapping clock pulses and the trigger signal generating portion controls trigger signals to ensure stable operation in both forward and reverse directions without requiring separate circuit structures for each direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bidirectional shift register uses complex circuit structure with separate structures for forward and reverse directions, then bidirectional operation is achieved, but device area and transistor size increase
Solution Approach 1:
The shift register uses a single unified circuit structure that can operate in both forward and reverse directions by controlling the phase sequence of clock signals. The same unit register circuits process signals bidirectionally depending on the clock phase sequence, eliminating the need for separate circuit structures for each direction and reducing overall device area.
Solution Approach 2:
The invention dynamically switches the operation direction by changing the phase sequence of clock signals rather than using fixed separate circuits. The clock signal generating portion can switch between normal phase sequence (forward operation) and inverted phase sequence (reverse operation), allowing the same hardware to adapt to different operational requirements.
2Area of stationary object
If bidirectional shift register uses simple circuit structure, then device area is reduced, but timing accuracy and operation stability deteriorate
Solution Approach 1:
The invention uses feedback mechanisms where the output of each unit register circuit is fed back to control the timing and sequencing of subsequent operations. The clock signal generating portion generates phased clock signals that provide timing feedback to ensure synchronized operation of all unit register circuits, maintaining stability despite the simplified circuit structure.
Solution Approach 2:
The clock signal generating portion preliminarily establishes the correct phase sequence before signal processing begins. By pre-synchronizing the clock phases and ensuring proper sequencing before bidirectional operation starts, the system prevents timing errors and maintains operational stability throughout the process.
3Speed
If clock pulses overlap during direction switching, then transition speed is improved, but through current increases
Solution Approach 1:
The invention uses periodic non-overlapping clock pulses with carefully controlled phases to drive the bidirectional operation. By using periodic clock signals with specific phase relationships (where each phase is offset by one clock period), the system achieves fast direction switching without continuous overlap, reducing power consumption while maintaining high-speed operation.
Solution Approach 2:
The clock signal generating portion provides slightly excessive phase coverage during transitions, where clock phases are arranged to ensure complete coverage of the transition period without full overlap. This partial overlap approach ensures reliable switching while minimizing the duration and extent of simultaneous clock pulse application, thereby reducing through current.
Data Source
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AI summary
A bidirectional shift register outputs pulses from a plurality of cascaded unit register circuits in a shift order which is one of a forward direction and a reverse direction. A λth stage of unit register circuit (38) has two set terminals connected to respective outputs of (λ-1)th and (λ+1)th stages and two reset terminals connected to respective outputs of (λ+2) th and (λ-2) th stages. The unit register circuit (38) sets, when a pulse is input to any one of the set terminals, a reference point N1 to an H level, and, when a pulse is input to any one of the reset terminals, N1 to an L level. The order of phase change of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched.