Bidirectional Shift Register for LCD Scan Pulse Control
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Solution Overview
Problem
Conventional shift registers in liquid crystal display devices output scan pulses in a fixed direction, limiting their versatility and adaptability to various liquid crystal display models.
Innovation Solution
A shift register design that includes multiple stages and dummy stages to output scan pulses in both forward and reverse directions, allowing for flexible control of scan pulse order through a scan direction controller, enabling operation in different liquid crystal display configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional shift register outputs scan pulses in a fixed direction, then the structure is simple, but the adaptability to various liquid crystal display models is poor
Solution Approach 1:
The shift register is designed to output scan pulses in both forward and reverse directions using the same stage structure. The dummy stages are configured to enable bidirectional operation, allowing the device to adapt to different liquid crystal display models (such as top-gate and bottom-gate configurations) without requiring structurally different designs for each application.
2Adaptability or versatility
If additional switching devices are added to change output order, then the adaptability improves, but the internal complexity increases
Solution Approach 1:
The dummy stages are designed to automatically provide the necessary control signals for bidirectional operation. The first dummy stage outputs a first dummy scan pulse to the first scan stage, and the second dummy stage outputs a second dummy scan pulse to the last scan stage, enabling the shift register to control its own output order without requiring external switching devices or additional control circuitry.
Data Source
AI summary
A shift register includes a plurality of scan stages to output scan pulses to a plurality of gate lines, a first dummy stage to output a first dummy scan pulse to a first of the plurality of scan stages, and a second dummy stage to output a second dummy scan pulse to a last of the plurality of scan stages.