Bi-Directional Shift Register Circuit for Leakage Current Suppression
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Solution Overview
Problem
Conventional bi-directional shift registers in gate line driving circuits for image display apparatuses suffer from malfunction due to leakage current, require unnecessary end pulse input, and are prone to noise interference, leading to display defects and increased costs.
Innovation Solution
The proposed bi-directional shift register design includes additional transistors to manage node voltages and eliminate the need for end pulse input, using transistors to discharge nodes and manage parasitic capacity, thereby preventing leakage current-induced malfunctions and noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional bi-directional shift register design is used, then display pattern change capability is achieved, but malfunction occurs due to leakage current
Solution Approach 1:
The patent extracts and addresses the leakage current problem by adding specific transistors (fifth transistor connected to first node, sixth transistor connected to second node) that actively discharge accumulated leakage charges. This removes the harmful leakage current effect from the system while preserving the bi-directional shift register's display pattern change capability.
Solution Approach 2:
The patent introduces intermediate discharge transistors as mediators between the floating nodes and ground. These transistors act as intermediaries to safely discharge leakage currents without affecting the normal operation of the main shift register transistors, thus resolving the reliability issue while maintaining adaptability.
2Adaptability or versatility
If conventional bi-directional shift register design is used, then shift direction switching is enabled, but end pulse input is required
Solution Approach 1:
The patent implements self-service by enabling the shift register to automatically manage its own state transitions. The added discharge transistors allow the circuit to self-reset and self-manage floating node states without requiring external end pulse inputs, thus simplifying the overall system while maintaining bidirectional shift capability.
Solution Approach 2:
Instead of using end pulses to actively reset the circuit state, the patent inverts the approach by allowing the circuit to naturally discharge through the added transistors. This passive discharge mechanism eliminates the need for active end pulse management, reducing device complexity while preserving shift direction switching functionality.
3Productivity
If conventional bi-directional shift register design is used, then signal transmission is achieved, but noise interference occurs
Solution Approach 1:
The patent converts the harmful effect of floating node susceptibility to noise into a beneficial discharge mechanism. By providing controlled discharge paths through the fifth and sixth transistors, the circuit actively manages the floating node states that would otherwise be vulnerable to noise, thus eliminating noise interference while maintaining signal transmission capability.
4Reliability
If additional transistors are added to suppress leakage current, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the shift register circuit into functional units with dedicated discharge transistors for each floating node. This segmentation allows the reliability improvement to be localized to specific circuit points without requiring a complete redesign of the entire shift register, thus minimizing the overall increase in device complexity while effectively suppressing leakage current.
Data Source
AI summary
Malfunction caused by leakage current of the transistor is prevented in the shift register in which the signal can be shifted bi-directionally. The bi-directional unit shift register includes a transistor Q1 between a clock terminal CK and an output terminal OUT, a transistor Q2 for discharging the output terminal OUT, and transistors Q3, Q4 for providing first and second voltage signals Vn, Vr, which are complementary to each other, to the first node or a gate node of the transistor Q1. Furthermore, a transistor Q5, having a gate connected to a second node or a gate node of the transistor Q2, for discharging the first node is arranged.


