Bidirectional Shift Register Voltage Stress Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional bidirectional shift registers in LCD driving circuits suffer from electrical degradation of transistors due to high voltage control signals, leading to potential circuit breakdown and operation failure, particularly in amorphous silicon components.
Innovation Solution
A bidirectional shift register design utilizing four control signal bus lines and clock signals with specific timing and phase characteristics to control forward and backward scanning operations, reducing voltage stress and enhancing reliability by optimizing the waveform and duration of control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If high level voltage control signals are used to control the bidirectional shift register, then the scanning direction can be controlled effectively, but transistor electrical degradation occurs leading to circuit breakdown
Solution Approach 1:
The patent applies periodic action by using AC signals instead of DC high level voltages to control the bidirectional shift register. The control signals periodically switch between high and low levels, achieving scanning direction control while avoiding continuous high voltage exposure that causes transistor degradation. This periodic switching maintains operational control while reducing cumulative electrical stress on the transistors.
Solution Approach 2:
The patent changes the parameter of control signals from DC high level voltage to AC signals with varying amplitude and phase. By modifying the voltage parameters dynamically - using different amplitude and phase combinations for forward and backward scanning - the patent achieves effective direction control while the varying parameters prevent sustained high voltage stress that leads to transistor degradation.
2Adaptability or versatility
If conventional two-way shift register is used with complementary control signals, then bidirectional scanning is achieved, but voltage stress causes transistor deterioration over time
Solution Approach 1:
The patent uses periodic AC control signals with different phases to achieve bidirectional scanning. Instead of using continuous complementary DC signals that maintain high voltage stress, the AC signals periodically vary in amplitude and phase, enabling forward and backward scanning while reducing continuous voltage stress on the transistors, thereby improving reliability.
Solution Approach 2:
The patent introduces dynamics by using AC signals with variable amplitude and phase rather than static DC control signals. The control signals dynamically adjust their parameters based on the required scanning direction, enabling versatile bidirectional operation while the dynamic nature of the signals prevents sustained high voltage exposure that causes transistor deterioration.
3Ease of operation
If high level voltage is continuously applied to control nodes, then scanning direction control is maintained, but electrical degradation leads to operation failure
Solution Approach 1:
The patent applies periodic AC control signals that continuously alternate between high and low levels rather than maintaining continuous high level voltage. This periodic action sustains the ability to control scanning direction while significantly extending the circuit's operational duration by preventing cumulative electrical degradation of the transistors.
Solution Approach 2:
The patent changes the control signal parameters from static high level voltage to dynamically varying AC signals. By continuously modifying the amplitude and phase parameters of the control signals, the patent maintains effective scanning direction control while extending the operational duration of the circuit through reduced sustained voltage stress on the transistors.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A bidirectional shift register includes first, second, third and fourth control signal bus lines for providing first, second, third and fourth control signals (Bi1, Bi2, Bi3, Bi4), respectively, and a plurality of shift register stages (302) electrically coupled in serial, each shift register stage (302) having a first input node (Bi) and a second input node (XBi), where the plurality of shift register stages (302) is grouped into a first section (321) and a second section (322), wherein the first (Bi) and second (XBi) input nodes of each shift register stage (302) in the first section (321) are electrically coupled to the first and second control signal bus lines for receiving the first (Bi1) and second (Bi2) control signals, respectively, and the first (Bi) and second (XBi) input nodes of each shift register stage (302) in the second section (322) are electrically coupled to the third and fourth control signal bus lines for receiving the third (Bi3) and fourth (Bi4) control signals, respectively.