Bidirectional Switch Gate Pad Arrangement for Resistance Equalization
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Solution Overview
Problem
Conventional bidirectional switches with a double gate structure experience significant differences in interconnect resistance between gate electrodes, leading to delays in switching and increased power loss, particularly at high switching frequencies due to uneven interconnect distances and resistances.
Innovation Solution
The arrangement of gate electrode pads is optimized such that the interconnect resistance between the first and second gate electrodes in each unit cell is made substantially equal, reducing the delay time and switching loss by ensuring uniform interconnect distances and resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate electrode pads are arranged at diagonally opposite positions to efficiently arrange four pads, then pad arrangement efficiency is improved, but interconnect resistance difference between first and second gate electrodes increases
Solution Approach 1:
The patent applies asymmetry by intentionally designing different pad arrangements for first and second gate electrodes. Specifically, the first gate electrode pad is positioned closer to the first gate electrode while the second gate electrode pad is positioned closer to the second gate electrode, creating asymmetric interconnect paths that compensate for the inherent resistance differences in the double gate structure.
Solution Approach 2:
The patent achieves equipotentiality by equalizing the interconnect resistance values between the first gate electrode and its pad, and between the second gate electrode and its pad. This is accomplished through careful positioning of the pads at specific distances from their respective gate electrodes, ensuring that both gates experience equivalent electrical conditions during switching operations.
2Loss of time
If interconnect resistance between gate electrodes is made substantially equal, then switching delay is reduced, but pad arrangement becomes more complex
Solution Approach 1:
The patent applies local quality by optimizing the interconnect resistance characteristics specifically at the gate electrode pad interfaces. Rather than uniformly distributing all pads, the design focuses on creating locally optimized interconnect paths where the resistance from each gate electrode to its respective pad is equalized, while other areas of the device maintain their functional layouts.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the positional parameters of the gate electrode pads relative to their corresponding gate electrodes. By varying the distances and orientations of the pads, the interconnect resistance values are tuned to achieve substantial equality, thereby minimizing switching delays without requiring complete redesign of the overall device architecture.
3Ease of manufacture
If conventional pad arrangement is used, then manufacturing is simpler, but power loss during switching increases at high frequencies
Solution Approach 1:
The patent applies equipotentiality to ensure that both gate electrodes experience equal interconnect resistance during switching operations. This equalization prevents timing mismatches between the gates, reducing unwanted voltage offsets and minimizing power loss during high-frequency switching, while maintaining a pad arrangement that remains manufacturable with standard processes.
Solution Approach 2:
The patent converts the potential harm of increased pad arrangement complexity into a benefit by demonstrating that the optimized pad positioning, while slightly more complex than conventional arrangements, delivers significant reductions in switching power loss at high frequencies, making the additional complexity worthwhile for high-performance applications.
Data Source
AI summary
A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.